Format Of The Processor Clock Control Register - NEC PD750004 User Manual

Figure 5-12. Format of the Processor Clock Control Register
Address
3 2
FB3H PCC3 PCC2 PCC1 PCC0
Symbol
1 0
PCC
CPU clock selection bit
(Operation with f
( ) is actual frequency at f
CPU clock frequency
0 0 = f
X
0 1 = f
X
1 0
= f
X
1 1
= f
X
(Operation with f
( ) is actual frequency at f
CPU clock frequency
0 0 = f
X
0 1
= f
X
1 0
= f
X
1 1
= f
X
Remarks 1. f
2. f
CPU operation mode control bits
0 0
Normal operation mode
0 1 HALT mode
1 0 STOP mode
1 1
Not to be set
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
= 6.0 MHz)
X
SCC3, SCC0 = 00
= 6.0 MHz
X
1 machine cycle
/64 (93.7 kHz) 10.7 µs
/16 (375 kHz) 2.67 µs
/8 (750 kHz) 1.33 µs
/4 (1.5 MHz) 0.67 µs
= 4.19 MHz)
X
SCC3, SCC0 = 00
= 4.19 MHz
X
1 machine cycle
/64 (65.5 kHz) 15.3 µs
3.81 µs
/16 (262 kHz)
/8 (524 kHz) 1.91 µs
0.95 µs
/4 (1.05 MHz)
: Output frequency from the main system clock oscillator
X
: Output frequency from the subsystem clock oscillator
XT
SCC3, SCC0 = 01 or 11
( ) is actual frequency at f
XT
CPU clock frequency 1 machine cycle
= f /4 (8.192 kHz)
XT
SCC3, SCC0 = 01 or 11
( ) is actual frequency at f
XT
CPU clock frequency 1 machine cycle
= f /4 (8.192 kHz)
XT
= 32.768 kHz
122 µs
= 32.768 kHz
122 µs
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