Interrupt Timing Specify Register Format - NEC PD78052 User Manual

Pd78054 series; pd78054y series 8-bit single-chip microcontrollers
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78054Y Subseries)
(4) Interrupt timing specify register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level
status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
Figure 17-6. Interrupt Timing Specify Register Format (1/2)
Symbol
7
<6>
<5>
SINT
0
CLD
SIC SVAM CLC WREL WAT1 WAT0
R/W
WAT1
Wait and Interrupt Control
WAT0
0
0
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
(keeping clock output in high impedance)
0
1
Setting prohibited
1
0
Used in I
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 8 clock
pulses are input.)
1
1
Used in I
Generates interrupt service request at rising edge of 9th SCK0 clock cycle.
(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are
output. In the case of slave device, makes SCL output low to request wait state after 9 clock
pulses are input.)
R/W
WREL
Wait Sate Cancellation Control
0
Wait state has been cancelled.
Cancels wait state. Automatically cleared to 0 when the state is cancelled.
1
(Used to cancel wait state by means of WAT0 and WAT1.)
CLC
R/W
Clock Level Control
2
0
Used in I
C bus mode.
Make output level of SCL pin low unless serial transfer is being performed.
2
1
Used in I
C bus mode.
Make SCL pin enter high-impedance state unless serial transfer is being performed.
(except for clock line which is kept high)
Used to enable master device to generate start condition and stop condition signals.
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When not using the I
354
<4>
<3>
<2>
1
0
2
C bus mode. (8-clock wait)
2
C bus mode. (9-clock wait)
Note 2
2
C mode, set CLC to 0.
Address
After Reset
R/W
FF63H
00H
R/W
Note 1

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