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Instruction
Mnemonic
Group
A, #byte
saddr, #byte
A, r
r, A
A, saddr
OR
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
8-bit
XOR
operation
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
CMP
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
CHAPTER 27 INSTRUCTION SET
Clock
Operands
Byte
Note 1
2
4
3
6
Note 3
2
4
2
4
2
4
3
8
1
4
2
8
2
8
2
8
2
4
3
6
Note 3
2
4
2
4
2
4
3
8
1
4
2
8
2
8
2
8
2
4
3
6
Note 3
2
4
2
4
2
4
3
8
1
4
2
8
2
8
2
8
Operation
Note 2
–
A
A
byte
8
(saddr)
(saddr)
byte
–
A
A
r
–
r
r
A
5
A
A
(saddr)
9 + n
A
A
(addr16)
5 + n
A
A
(HL)
9 + n
A
A
(HL + byte)
9 + n
A
A
(HL + B)
9 + n
A
A
(HL + C)
–
A
A
byte
8
(saddr)
(saddr)
byte
–
A
A
r
–
r
r
A
5
A
A
(saddr)
9 + n
A
A
(addr16)
5 + n
A
A
(HL)
9 + n
A
A
(HL + byte)
9 + n
A
A
(HL + B)
9 + n
A
A
(HL + C)
–
A – byte
8
(saddr) – byte
–
A – r
–
r – A
5
A – (saddr)
9 + n
A – (addr16)
5 + n
A – (HL)
9 + n
A – (HL + byte)
9 + n
A – (HL + B)
9 + n
A – (HL + C)
) selected by the processor clock
CPU
Flag
Z AC CY
567
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