Block Diagram - NEC PD78052 User Manual

1.7 Block Diagram

TO0/P30
16-bit TIMER/
TI00/INTP0/P00
EVENT COUNTER
TI01/INTP1/P01
TO1/P31
8-bit TIMER/
EVENT COUNTER 1
TI1/P33
TO2/P32
8-bit TIMER/
EVENT COUNTER 2
TI2/P34
WATCHDOG TIMER
WATCH TIMER
SI0/SB0/P25
SERIAL
SO0/SB1/P26
INTERFACE 0
SCK0/P27
SI1/P20
SO1/P21
SERIAL
SCK1/P22
INTERFACE 1
STB/P23
BUSY/P24
SI2/RxD/P70
SERIAL
SO2/TxD/P71
INTERFACE 2
SCK2/ASCK/P72
ANI0/P10-
ANI7/P17
AV
DD
A/D CONVERTER
AV
SS
AV
REF0
ANO0/P130,
ANO1/P131
D/A CONVERTER
AV
SS
AV
REF1
INTP0/P00- INTERRUPT
INTP6/P06
CONTROL
BUZ/P36
BUZZER OUTPUT
CLOCK OUTPUT
PCL/P35
CONTROL
Remarks 1. The internal ROM and RAM capacities depend on the product.
2. Pin connection in parentheses is intended for the PD78P054, 78P058.
CHAPTER 1 OUTLINE ( PD78054 Subseries)
78K/0
ROM
CPU CORE
RAM
V V
DD SS
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 12
PORT 13
REAL-TIME
OUTPUT PORT
EXTERNAL
ACCESS
SYSTEM
CONTROL
IC
(V )
PP
P00
P01-P06
P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P120-P127
P130, P131
RTP0/P120-
RTP7/P127
AD0/P40-
AD7/P47
A8/P50-
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
XT1/P07
XT2
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