NEC PD78052 User Manual page 565

Instruction
Mnemonic
Group
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
16-bit
MOVW AX, sfrp
data
sfrp, AX
transfer
AX, rp
rp, AX
AX, !addr16
!addr16, AX
XCHW AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
ADD
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
8-bit
operation
A, #byte
saddr, #byte
A, r
r, A
A, saddr
ADDC
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.
2. When an area except the internal high-speed RAM area is accessed.
3. Only when rp = BC, DE or HL
4. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
CHAPTER 27 INSTRUCTION SET
Clock
Operands Byte
Note 1
3 6
4 8
4 –
2 6
2 6
2 –
2 –
Note 3
1 4
Note 3
1 4
3 10
3 10 12 + 2m (addr16)
Note 3
1 4
2 4
3 6
Note 4
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 4
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
Operation
Note 2
– rp word
10 (saddrp) word
10 sfrp word
8 AX (saddrp)
8 (saddrp) AX
8 AX sfrp
8 sfrp AX
– AX rp
– rp AX
12 + 2n AX (addr16)
AX
– AX rp
– A, CY A + byte
8 (saddr), CY (saddr) + byte
– A, CY A + r
– r, CY r + A
5 A, CY A + (saddr)
9 + n A, CY A + (addr16)
5 + n A, CY A + (HL)
9 + n A, CY A + (HL + byte)
9 + n A, CY A + (HL + B)
9 + n A, CY A + (HL + C)
– A, CY A + byte + CY
8 (saddr), CY (saddr) + byte + CY
– A, CY A + r + CY
– r, CY r + A + CY
5 A, CY A + (saddr) + CY
9 + n A, CY A + (addr16) + CY
5 + n A, CY A + (HL) + CY
9 + n A, CY A + (HL + byte) + CY
9 + n A, CY A + (HL + B) + CY
9 + n A, CY A + (HL + C) + CY
) selected by the processor clock
CPU
Flag
Z AC CY
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