Table of Contents
Advertisement
Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
Revision ID/ Class Code Registers
2
Offset
Bit
3
1
Name
Operation
Reset
I/O Base Register
Offset
Bit
3
1
Name
Operation
Reset
2-52
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
REVID
Revision ID. This register identifies the Raven revision
level. This register is duplicated in the MPC Registers.
CLASS
Class Code. This register identifies Raven as the
following:
Base Class Code
Subclass Code
Program Class Code
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
IOBA
R/W
$0000
This register controls the mapping of the RavenMPIC control registers in
PCI I/O space.
$08
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
CLASS
R
$060000
$06
$00
$00
$10
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
IOBASE
Computer Group Literature Center Web Site
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
REVID
R
$02
PCI Bridge Device
PCI Host Bridge
Not Used
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$0000
Advertisement
Table of Contents
