Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1272

2
I C Controller
0
Field
Reset
R/W
Addr
Table 39-4 describes the I2CER/I2CMR fields.
Bits Name
0–2 — Reserved and should be cleared.
3 TXE Tx error. Set when an error occurs during transmission.
4 — Reserved and should be cleared.
5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Two
character times must elapse to guarantee that all data has been sent.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.
39.4.5 I C Command Register (I2COM)
2
2
The I C command register, shown in
slave mode.
0
Field STR
Reset
R/W
Addr
Table 39-5 describes I2COM fields.
Bits Name
0 STR Start transmit. In master mode, setting STR causes the I
2
I C Tx buffers if they are ready. In slave mode, setting STR when the I
to load the Tx data register from the I
byte that matches the slave address with R/W = 1. STR is always read as a 0.
39-8
2
—
0x0x11870(I2CER)/0x0x11874 I2CMR)
2
Figure 39-9. I C Event/Mask Registers (I2CER/I2CMR)
Table 39-4. I2CER/I2CMR Field Descriptions
Figure 39-10, is used to start I
1 2
2
Figure 39-10. I C Command Register (I2COM)
Table 39-5. I2COM Field Descriptions
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3 4
TXE —
0000_0000
R/W
Description
2
C transfers and to select master or
3 4
—
0000_0000
R/W
0x0x1186C
Description
2
C controller to start sending data from the
2
C Tx buffer and start sending when it receives an address
5 6
BSY TXB
5 6
2
C controller is idle causes it
Freescale Semiconductor
7
RXB
7
M/S