Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1294

Parallel I/O Ports
Table 40-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued)
PIN
PDIRC = 1 (Output)
PC10 FCC1: TxD[2]
UTOPIA 16
PC9 FCC1: TxD[1]
UTOPIA 16
PC8 FCC1: TxD[0]
UTOPIA 16
PC7 TDM_C1: L1RQ
PC6 TDM_C1: L1CLKO
PC5 FCC2: TxClav
UTOPIA, slave
PC4 FCC2: RxEnb
UTOPIA, master
PC3 FCC2: TxD[2]
UTOPIA 8
PC2 FCC2: TxD[3]
UTOPIA 8
PC1 BRG6: BRGO
PC0 BRG7: BRGO
40-16
PSORC = 0
PDIRC = 0 (Input)
1
SCC3: CD
SCC3: RENA
Ethernet
1
SCC4: CTS
SCC4: CLSN
Ethernet
(primary option)
1
SCC4: CD
SCC4: RENA
Ethernet
FCC1: CTS
FCC1: CD
1 1
FCC2: TxClav
UTOPIA, master
1 1
FCC2: RxEnb
UTOPIA, slave
1
FCC3: CTS
1
FCC3: CD
IDMA2: DREQ
IDMA1: DREQ
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Pin Function
Defaul
PDIRC = 1 (Output)
t Input
GND SI1: L1ST4
strobe
by PC3 SI2: L1ST1
strobe
GND SI2: L1ST2
Strobe
GND FCC1: TxAddr[2]
MPHY master,
multiplexed: polling
GND FCC1: RxAddr[2]
MPHY, master,
multiplexed polling
GND SI2: L1ST3
Strobe
GND SI2: L1ST4
Strobe
GND IDMA2: DACK
GND
GND TDM_A2: L1RQ
GND TDM_A2: L1CLKO
PSORC = 1
PDIRC = 0 (Input or Defaul
Inout if Specified) t Input
1,3
FCC2: RxD[3]
UTOPIA
(secondary option)
TDM_A2:
L1TSYNC/GRANT
(secondary option)
SCC3: CTS
2
SCC3:CLSN
(secondary option)
1 1,3
FCC1: TxAddr[2]
MPHY, slave,
multiplexed polling
1,3
FCC1: TxClav1
MPHY, master, direct
polling
1
FCC2: TxAddr[2]
MPHY, slave,
multiplexed polling
1 1,3
FCC1: RxAddr[2]
MPHY, slave,
multiplexed polling)
1,3
FCC1: RxClav1
MPHY, master, direct
polling
1
FCC2: RxAddr[2]
MPHY, slave,
multiplexed polling
FCC2: CTS
FCC2: CD
SCC4: CTS
2
SCC4: CLSN
(secondary option)
IDMA2: DONE
Inout
2
SPI: SPISEL
Inout
(secondary option)
SMC2: SMSYN
(secondary option)
Freescale Semiconductor
GND
GND
GND
GND
GND
GND
GND
GND
V
DD
GND