Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1320

Breakpoint. A programmable event that forces the core to take a breakpoint exception.
Burst. A bus transfer whose data phase consists of a sequence of transfers. For example,
Bus parking. A feature that optimizes the use of the bus by allowing a device to retain bus
C
Cache. High-speed memory component containing recently-accessed data and/or
Cache coherency. An attribute in which an accurate and common view of memory is
Cache flush. An operation that removes from a cache any data from a specified address
Caching-inhibited. A memory update policy in which the cache is bypassed and the load
Cast-outs. Cache blocks that must be written to memory when a cache miss causes a cache
Changed bit. One of two page history bits found in each page table entry (PTE). The
Clear. To cause a bit or bit field to register a value of zero. The opposite of set.
Context synchronization. An operation that ensures that all instructions in execution
Copy-back. An operation in which modified data in a cache block is copied back to
Glossary-2
Although the architecture does not prescribe the exact behavior for when results
are allowed to be boundedly undefined, the results of executing instructions in
contexts where results are allowed to be boundedly undefined are constrained to
ones that could have been achieved by executing an arbitrary sequence of defined
instructions, in valid form, starting in the state the machine was in before
attempting to execute the given instruction.
on a 64-bit bus, a four-beat burst can transfer four, 64-bit double words.
mastership without having to rearbitrate.
instructions (subset of main memory).
provided to all devices that share the a memory system. Caches are coherent if a
processor performing a read from its cache is supplied with data corresponding to
the most recent value written to memory or to another processor's cache.
range. This operation ensures that any modified data within the specified address
range is written back to main memory. This operation is generated typically by a
Data Cache Block Flush (dcbf) instruction.
or store is performed to or from main memory.
block to be replaced.
processor sets the changed bit if any store is performed into the page. See also
Page access history bits and Referenced bit.
complete past the point where they can produce an exception, that all instructions
in execution complete in the context in which they began execution, and that all
subsequent instructions are fetched and executed in the new context. Context
synchronization may result from executing specific instructions (such as isync or
rfi) or when certain events occur (such as an exception).
memory.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor