Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1304

Reference Manual (Rev 1) Errata
4.3.2.1, 4-28
4.3.2.2, 4-31
4.3.2.8, 4-38
5.3, 5-6
5.4.1, 5-10
7.2.8.1.1, 7-17
Timing Comments
7.2.8.1.2, 7-17
Timing Comments
B-2
The bit definitions should be reversed for BCR[DAM] in Table 4-9. They should
appear as follows:
10 DAM Delay all masters. Applies to all the masters on the bus (CPU, EXT, CPM).
This bit is similar to BCR[EXDD] but with opposite polarity.
0 The memory controller asserts CS on the cycle following the assertion of
TS when accessing an address space controlled by the memory
controller.
1 The memory controller inserts one wait state between the assertion of TS
and the assertion of CS when accessing an address space controlled by
the memory controller.
In Table 4-10, the description of PRKM = 0010 contains an incorrect
cross-reference. It should state, "See Section 29.7.1, "FCC Function Code
Registers (FCRx)."
In Table 4-14 the reserved field should be bits 26–28 (as shown in Figure 4-30),
not 26–29. Bit 29 is SWE (software watchdog enable).
In Table 5-4, add the following to the description of CSRE:
Note: When the core is disabled, CSRE must be cleared.
In Table 5-7, add the following to the description of CS10PC:
Note: During the reset configuration sequence, the BCTL1/CS10 pin toggles like
POE of the 60x bus GPCM, regardless of the configuration of the reset
configuration word. After the reset configuration sequence, the BCTL1/CS10 pin
behaves according to the configuration of SIUMCR[CS10PC].
Replace the description of TA input assertion with the following:
Assertion depends on whether or not the PCI controller can initiate 60x bus global
transactions when the address retry mechanism is in use:
PCI controller is not used or cannot initiate global transactions—Assertion must
occur at least one cycle following AACK for the current transaction; otherwise,
assertion may occur at any time during the assertion of DBB. The system can
withhold assertion of TA to indicate that the PowerQUICC II should insert wait
states to extend the duration of the data beat.
PCI controller can initiate global transactions—Assertion must occur at least one
clock cycle following AACK for the current transaction and at least one clock
cycle after ARTRY can be asserted.
Replace the description of TA output assertion with the following:
Assertion depends on whether or not the PCI controller can initiate 60x bus global
transactions when the address retry mechanism is in use:
PCI controller is not used or cannot initiate global transactions—Assertion must
occur at least one cycle following AACK for the current transaction; occurs on the
clock in which the current data transfer can be completed.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor