Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1317

and transmitted a byte at a time with lsb first:
first r_stuv_ghij_klmn
39.4.3, 39-8
0–7 DIV
40-5, 40-10
Pin
PDIRA = 1 (Output)
PA9 SMC2: SMTXD
40-5, 40-16
Freescale Semiconductor
In Table 39-3, the description of DIV should read as follows (changes appear in
boldface):
Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I
of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty
cycle. DIV must be programmed to a minimum value of 3 if the digital filter is disabled
(I2MOD[FLT] = 0) and 6 if it is enabled (I2MOD[FLT] = 1).
In Table 40-5, add TDM_A1:L1TXD to PA9 in the column for PSORA = 1 and
PDIRA = 0, as shown below:
PSORA = 0
PDIRA = 0 (Input)
In Table 40-7, the note attached to SPI: SPISEL at PC1 is incorrect. It should refer
to note 2 ("available only when the primary option for this function is not used")
and not note 3.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
last
Pin Function
Default
PDIRA = 1 (Output)
Input
TDM_A1: L1TXD[0]
Output, nibble
Reference Manual (Rev 1) Errata
2
C clock generator. The output
PSORA = 1
PDIRA = 0 (Input, or Default
In/out if Specified) Input
TDM_A1: L1TXD GND
Inout, serial
B-15