Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1327

Supervisor mode. The privileged operation state of a processor. In supervisor mode,
Synchronization. A process to ensure that operations occur strictly in order. See Context
Synchronous exception. An exception that is generated by the execution of a particular
System memory. The physical memory available to a processor.
T
Time-division multiplex (TDM). A single serial channel used by several channels taking
TLB (translation lookaside buffer) A cache that holds recently-used page table entries.
Throughput. The measure of the number of instructions that are processed per clock cycle.
U
UISA (user instruction set architecture). The level of the architecture to which user-level
User mode. The unprivileged operating state of a processor used typically by application
V
VEA (virtual environment architecture). The level of the architecture that describes the
Virtual address. An intermediate address used in the translation of an effective address to
Virtual memory. The address space created using the memory management facilities of
W
Watchpoint. An event that is reported, but does not change the timing of the machine.
Word. A 32-bit data element. Note that on other processors a word may be a different size.
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software, typically the operating system, can access all control registers and can
access the supervisor memory space, among other privileged operations.
synchronization and Execution synchronization.
instruction or instruction sequence. There are two types of synchronous
exceptions, precise and imprecise.
turns.
software should conform. The UISA defines the base user-level instruction set,
user-level registers, data types, floating-point memory conventions and exception
model as seen by user programs, and the memory and programming models.
software. In user mode, software can only access certain control registers and can
access only user memory space. No privileged operations can be performed. Also
referred to as problem state.
memory model for an environment in which multiple devices can access memory,
defines aspects of the cache model, defines cache control instructions, and defines
the time-base facility from a user-level perspective. Implementations that conform
to the PowerPC VEA also adhere to the UISA, but may not necessarily adhere to
the OEA.
a physical address.
the processor. Program access to virtual memory is possible only when it
coincides with physical memory.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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