Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1289

Table 40-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued)
Pin
PDIRA = 1 (Output)
PA9 SMC2: SMTXD
PA8
PA7
PA6
PA5 SCC2: RSTRT
PA4 FCC2: RxAddr[1]
MPHY master
PA3 FCC2: RxAddr[0]
MPHY master
PA2 FCC2: TxAddr[0]
MPHY master
PA1 FCC2: TxAddr[1]
MPHY master
PA0 SCC1: RSTRT
1
Not available on the MPC8250.
2
MSNUM[0–4] is the sub-block code of the peripheral controller using SDMA; MSNUM[5] indicates which section,
transmit or receive, is active during the transfer. See
(PDTEM and LDTEM)."
3
.25µm (HiP4) devices only: available only when the primary option for this function is not used.
Table 40-6 shows the port B pin assignments.
Freescale Semiconductor
PSORA = 0
PDIRA = 0 (Input)
SMC2: SMRXD
(primary option)
SMC2: SMSYN
(primary option)
1,3
FCC1: RxPrty
UTOPIA
(secondary option)
1
SCC2: REJECT
1
CLK19
1
CLK20
1
SCC1: REJECT
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Pin Function
Defaul
PDIRA = 1 (Output)
t Input
TDM_A1: L1TXD[0]
Output, nibble
by PD4
by PC0
GND FCC2: RxAddr[2]
MPHY master
VDD
GND IDMA4: DACK
GND IDMA3: DACK
VDD
FCC2: TxAddr[2]
MPHY master
Section 19.2.4, "SDMA Transfer Error MSNUM Registers
Parallel I/O Ports
PSORA = 1
PDIRA = 0 (Input, or Defaul
Inout if Specified) t Input
TDM_A1: L1TXD
Inout, serial
TDM_A1: L1RXD[0]
Input, nibble
TDM_A1: L1RXD
Inout, serial
TDM_A1:
L1TSYNC/GRANT
TDM_A1: L1RSYNC
1
IDMA4: DREQ
IDMA4: DONE
Inout
TDM_A2: L1RXD[1]
Nibble
IDMA3: DONE
Inout
1
IDMA3: DREQ
GND
GND
GND
GND
GND
VDD
GND
VDD
GND
40-11