Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1314

Reference Manual (Rev 1) Errata
33.4.1.1, 33-29
0x0E IASNCCTR
0x0F IASNC
33.4.4.1.1, 33-29
5
33.4.4.1.2, 33-30
0
Field TSTF
2 GTE
3 TRQS
33.4.4.2, 33-35
0x2C —
0x30 LINK_DCBO
33.4.5.1.2, 33-40
Field LSTF
5 LDC
B-12
Add the following two rows to the bottom of Table 33-5:
Byte Required for optional TRL Service Latency enhancement only.
IMA APC Scheduled Number of Cells Counter - Number of cells passed to
the groups links upon request. Initialize to IASNC.
Byte Required for optional TRL Service Latency enhancement only.
IMA APC Scheduled Number of Cells - reset for IASNCtr. Number of cells
passed to the groups links upon request. Recommended value is 1.
Add ISIE to Figure 33-14 and Table 33-6, as shown in the following:
0
Field
ISIE Required for optional TRL Service Latency enhancement only.
IMA Scheduler Split Iterations Enable
0 - APC is not split, TRL completes round robin distribution of cells.
1 - APC split, both TRL and non-TRL requests distribute cells to the transmit queues.
Add GTE and TRQS to Figure 33-15 and Table 33-7, as shown in the following:
1 2
TIMSTF GTE
Go to end flag - TRL has requested 2 times before round robin distribution has completed or
link will underrun and is still due a cell from round robin distribution. Microcode managed
parameter initialize to 0. Used for optional TRL Service Latency enhancement only.
TRL Request - TRL has requested therefore 1 round robin distribution of cells and is yet to be
completed. Microcode managed parameter initialize to 0. Used for optional TRL Service
Latency enhancement only.
In Table 33-10 replace the descriptions of offsets 0x2C and 0x30 with the
following:
Word
Word
Add LDC to Figure 33-22 and Table 33-17, as shown in the following:
0 1 2
LIMSTF LSTLFIP
Link Due Cell. Link is due cell from round robin distribution. Microcode managed parameter
initialize to 0. Used for optional TRL Service Latency enhancement only.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2 3
— TXSC
3 4
TRQS ELX
Reserved. Must be initialized to zero at group startups.
Link DCB overflow interrupt indication. Bit array identifying which links
have issued a link DCB overflow (DCBO) interrupt. This parameter
ensures that only one DCBO interrupt is generated per event.
Microcode managed parameter. Initialize to zero at group startup.
3 4
LGSU TQSU
4 5 6
ISIE CTC
5 6
— ICH ICPCA
5 6
LDC —
Freescale Semiconductor
7
ICPC
7
7