Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1273

Bits Name
1–6 — Reserved and should be cleared.
7 M/S Master/slave. Configures the I
2
0 I
2
1 I
2
39.5 I C Parameter RAM
2
The I C controller parameter table is used for the general I
general-purpose parameter RAM. The CP accesses the I
pointer (I2C_BASE) located in the parameter RAM; see
parameter table can be placed at any 64-byte aligned address in the dual-port RAM's general-purpose area
(banks 1–8, 11 and 12). The user must initialize certain parameter RAM values before the I
the CP initializes the other values. Software usually does not access parameter RAM entries once they are
initialized; they should be changed only when the I
Table 39-6 shows the I
1
Offset Name
0x00 RBASE
0x02 TBASE
0x04 RFCR
0x05 TFCR
0x06 MRBLR
0x08 RSTATE
0x0C RPTR
Freescale Semiconductor
Table 39-5. I2COM Field Descriptions
2
C is a slave.
C is a master.
2
C parameter memory map.
2
Table 39-6. I C Parameter RAM Memory Map
Width
Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM.
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
Hword
allocated for the Tx and Rx sections of the I
2
enabling the I C. Furthermore, do not configure BD tables of the I
other active controller's parameter RAM. RBASE and TBASE should be divisible by
eight.
Byte Rx/Tx function code registers. The function code registers contain the transaction
specification associated with SDMA channel accesses to external memory. See
Byte
Figure 39-11 and Table
Hword Maximum receive buffer length. Defines the maximum number of bytes the
PowerQUICC II writes to a Rx buffer before moving to the next buffer. The
PowerQUICC II writes fewer bytes to the buffer than the MRBLR value if an error or
end-of-frame occurs. Buffers should not be smaller than MRBLR.
Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be
sent is specified in TxBD[Data Length].
MRBLR is not intended to be changed while the I
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next RxBD.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
2
the I C receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
2
Word Rx internal state.
Word Rx internal data pointer
in the buffer to be accessed.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
C controller to operate as a master or a slave.
2
C parameters and is similar to the SCC
2
C parameter table using a user-programmed
Section 14.5.2, "Parameter RAM."
2
C is inactive.
Description
2
C. Initialize RBASE/TBASE before
39-7.
Reserved for CP use.
2
is updated by the SDMA channels to show the next address
The I
2
C is enabled;
2
C to overlap any
2
C is operating. However it can be
2
I C Controller
2
C
39-9