Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 1324

Munging. A modification performed on an effective address that allows it to appear to the
Most-significant bit (msb). The highest-order bit in an address, registers, data element, or
Most-significant byte (MSB). The highest-order byte in an address, registers, data
N
No-op. No-operation. A single-cycle operation that does not affect registers or generate
O
OEA (operating environment architecture). The level of the architecture that describes
Optional. A feature, such as an instruction, a register, or an exception, that is defined by
Out-of-order. An aspect of an operation that allows it to be performed ahead of one that
Out-of-order execution. A technique that allows instructions to be issued and completed
Overflow. An error condition that occurs during arithmetic operations when the result
P
Pace control. Controls the rate of the data flow between a master and slave.
Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned
Page fault. A page fault is a condition that occurs when the processor attempts to access a
Glossary-6
processor that individual aligned scalars are stored as little-endian values, when
in fact it is stored in big-endian order, but at different byte addresses within double
words. Note that munging affects only the effective address and not the byte order.
Note also that this term is not used by the PowerPC architecture.
instruction encoding.
element, or instruction encoding.
bus activity.
PowerPC memory management model, supervisor-level registers,
synchronization requirements, and the exception model. It also defines the
time-base feature from a supervisor-level perspective. Implementations that
conform to the PowerPC OEA also conform to the PowerPC UISA and VEA.
the PowerPC architecture but not required to be implemented.
may have preceded it in the sequential model, for example, speculative operations.
An operation is said to be performed out-of-order if, at the time that it is
performed, it is not known to be required by the sequential execution model. See
In-order.
in an order that differs from their sequence in the instruction stream.
cannot be stored accurately in the destination register(s). For example, if two
32-bit numbers are multiplied, the result may not be representable in 32 bits.
on a 4-Kbyte boundary.
memory location that does not reside within a page not currently resident in
physical memory. On processors that implement the PowerPC architecture, a page
fault exception condition occurs when a matching, valid page table entry (PTE[V]
= 1) cannot be located.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor