Intel 500 - DATASHEET REV 003 Datasheet
  1. Manuals
  2. Brands
  3. Intel Manuals
  4. Computer Hardware
  5. 500 - DATASHEET REV 003
  6. Datasheet
Intel 500 - DATASHEET REV 003 Datasheet

Intel 500 - DATASHEET REV 003 Datasheet

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Δ
Intel® Celeron® Processor 500
Series
Datasheet
For Platforms Based on Mobile Intel® 965 Express Chipset Family
January 2008
Revision 003
Document Number: 317665-003

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the 500 - DATASHEET REV 003 and is the answer not in the manual?

Questions and answers

Related Manuals for Intel 500 - DATASHEET REV 003

Summary of Contents for Intel 500 - DATASHEET REV 003

  • Page 1 Δ Intel® Celeron® Processor 500 Series Datasheet For Platforms Based on Mobile Intel® 965 Express Chipset Family January 2008 Revision 003 Document Number: 317665-003...
  • Page 2 APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

  • Page 3: Table Of Contents

    Processor Pinout and Pin List ................34 Alphabetical Signals Reference ................53 Thermal Specifications .................... 61 Thermal Diode ....................62 5.1.1 Thermal Diode Offset ................62 Intel® Thermal Monitor..................64 Digital Thermal Sensor..................66 Out of Specification Detection ................66 PROCHOT# Signal Pin ..................67 Datasheet...
  • Page 4 Figures Package-Level Low-Power States ................11 Core Low-Power States .....................12 Active VCC and ICC Loadline Standard Voltage .............26 1-MB Fused Micro-FCPGA Processor Package Drawing (1 of 2) ........30 1-MB Fused Micro-FCPGA Processor Package Drawing (2 of 2) ........31 1-MB Micro-FCPGA Processor Package Drawing (1 of 2) ..........32 1-MB Micro-FCPGA Processor Package Drawing (2 of 2) ..........33 Tables Coordination of Core-Level Low-Power States at the Package Level .........11...
  • Page 5 Revision History Document Revision Description Date Number Number 317666 -001 Initial Release June 2007 317666 -002 Corrected Figures 4, 5, 6, & 7 November 2007 317665 -003 Added the Intel Celeron processor 560 January 2008 § Datasheet...
  • Page 6 Datasheet...

  • Page 7: Introduction

    • Architectural and performance enhancements of the Core microarchitecture. Note: Unless specified otherwise, all references to the processor in this document are references to the Celeron processor 500 series with a 533-MHz FSB on Mobile Intel 965 Express Chipset family-based systems. Datasheet...

  • Page 8: Terminology

    XXXX means that the specification or value is yet to be determined. Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ AGTL+ signaling technology on some Intel processors. Front Side Bus Refers to the interface between the processor and system core logic (also (FSB) known as the chipset components).

  • Page 9: References

    316274 Intel® I/O Controller Hub 8(ICH8) Family Datasheet 313056 Intel® I/O Controller Hub 8(ICH8) Family Specification Update 313057 Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z...
  • Page 10 Introduction Datasheet...

  • Page 11: Low Power Features

    These package states include Normal, Stop Grant, Stop Grant Snoop, Sleep, and Deep Sleep. The processor’s central power management logic enters a package low-power state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the Intel 965 Express Chipset family.

  • Page 12: Core Low-Power States

    A System Management Interrupt (SMI) A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/AutoHALT Powerdown state. See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information.

  • Page 13: C1/Mwait Powerdown State

    Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information.

  • Page 14: Stop Grant Snoop State

    Low Power Features Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in the Stop-Grant state, the processor services snoops and latch interrupts delivered on the FSB.

  • Page 15: Deep Sleep State

    Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings.
  • Page 16 Low Power Features Datasheet...

  • Page 17: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor has many V (power) and V (ground) inputs. All power pins must be connected to V power planes while all V pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop.

  • Page 18: Voltage Identification Definition

    Electrical Specifications Table 2. Voltage Identification Definition (Sheet 1 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000...
  • Page 19 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375...
  • Page 20 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625...

  • Page 21: Catastrophic Thermal Protection

    Electrical Specifications Table 2. Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures.

  • Page 22: Fsb Frequency Select Signals (Bsel[2:0])

    Electrical Specifications For testing purposes, route the TEST3 and TEST5 signals through a ground referenced = 55-Ω trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection. FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

  • Page 23: Cmos Signals

    Electrical Specifications Table 4. FSB Pin Groups (Sheet 2 of 2) Signal Group Type Signals Synchronous AGTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# to BCLK[1:0] A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, CMOS Input Asynchronous LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# Open Drain Output Asynchronous FERR#, IERR#, THERMTRIP# Open Drain I/O Asynchronous PROCHOT#...

  • Page 24: Processor Dc Specifications

    Electrical Specifications Table 5. Processor Absolute Maximum Ratings Symbol Parameter Unit Notes Processor storage °C 2, 3, 4 STORAGE temperature Any processor supply voltage -0.3 1.55 with respect to V AGTL+ buffer DC input -0.1 1.55 inAGTL+ voltage with respect to V CMOS buffer DC input -0.1 1.55...
  • Page 25 Electrical Specifications Table 6. DC Voltage and Current Specifications Symbol Parameter Unit Notes for processors Processor Frequency Die Variant Number 1-M Fused 34.5 1.73 GHz 32.0 1-M Fused 34.5 1.86 GHz 32.0 3, 4 1-M Fused 34.5 2.00 GHz 32.0 1-M Fused 34.5 2.13 GHz...

  • Page 26: Active Vcc And Icc Loadline Standard Voltage

    Electrical Specifications Figure 3. Active V and I Loadline Standard Voltage Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. CC, DC 10 mV= RIPPLE CC, DC +/-V nom * 1.5% = VR St. Pt. Error 1/ N o t e 1 / V S e t P o i n t E r r o r T o l e r a n c e i s p e r b e l o w : T o l e r a n c e...

  • Page 27: Agtl+ Signal Group Dc Specifications

    Electrical Specifications Table 8. AGTL+ Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 GTLREF Reference Voltage 2/3 V Compensation Resistor 27.23 27.5 27.78 Ω COMP Termination Resistor Ω Input High Voltage GTLREF+0.10 +0.10 2, 6 Input Low Voltage -0.10 GTLREF-0.10...

  • Page 28: Cmos Signal Group Dc Specifications

    Electrical Specifications Table 9. CMOS Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 Input High Voltage 0.7*V +0.1 Input Low Voltage CMOS -0.10 0.00 0.3*V 2, 3 Output High Voltage 0.9*V +0.1 Output Low Voltage -0.10 0.1*V Output High Current...

  • Page 29: Package Mechanical Specifications And Pin Information

    Package Mechanical Specifications and Pin Information Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor has two variants, both available in a 478-pin Micro-FCPGA package. Package mechanical dimensions are shown in Figure 4 for the 1-MB fused variant and Figure 6 for the 1-MB variant.

  • Page 30: 1-Mb Fused Micro-Fcpga Processor Package Drawing (1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 4. 1-MB Fused Micro-FCPGA Processor Package Drawing (1 of 2) Bottom View op View Front View Side View ø 0.356 ø 0.254 Detail A Datasheet...

  • Page 31: 1-Mb Fused Micro-Fcpga Processor Package Drawing (2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 5. 1-MB Fused Micro-FCPGA Processor Package Drawing (2 of 2) 4X 7.00 4X 7.00 Side View 4X 5.00 Edge Keep Out Corner Keep Out Zone 4X Zone 4X op View 0.305±0.25 13.97 0.406 1.625 0.254 6.985...

  • Page 32: 1-Mb Micro-Fcpga Processor Package Drawing (1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 6. 1-MB Micro-FCPGA Processor Package Drawing (1 of 2) Bottom View op View Front View Side View ø 0.356 ø 0.254 Detail A Datasheet...

  • Page 33: 1-Mb Micro-Fcpga Processor Package Drawing (2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 7. 1-MB Micro-FCPGA Processor Package Drawing (2 of 2) 4X 7.00 4X 7.00 Side View 4X 5.00 Edge Keep Out Corner Keep Out Zone 4X Zone 4X op View 13.97 ø 0.305±0.25 1.625 ø...

  • Page 34: Processor Pinout And Pin List

    Package Mechanical Specifications and Pin Information Processor Pinout and Pin List Table 11 shows the top view pinout of the processor. Table 11. The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) SMI# FERR# A20M#...

  • Page 35: The Coordinates Of The Processor Pins As Viewed From The Top Of The Package (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Table 12. The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) BCLK[1] BCLK[0] THRMDA TEST6 BSEL[0] BSEL[1] THRMDC VCCA DBR# BSEL[2] TEST1 TEST3 VCCA PROCHO IERR# RSVD DPWR#...
  • Page 36 Package Mechanical Specifications and Pin Information This page is intentionally left blank. Datasheet...

  • Page 37: Pin Listing By Pin Name

    Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 2 of 15) (Sheet 1 of 15) Signal Pin Name Direction Signal Number Buffer Type Pin Name Direction Number Buffer Type Input/ A[27]#...
  • Page 38 Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 3 of 15) (Sheet 4 of 15) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Input/ Input/...
  • Page 39 Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 5 of 15) (Sheet 6 of 15) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Input/ Input/...
  • Page 40 Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 7 of 15) (Sheet 8 of 15) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type RS[0]# Common Clock...
  • Page 41 Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 9 of 15) (Sheet 10 of 15) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type AE15 Power/Other...
  • Page 42 Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 11 of 15) (Sheet 12 of 15) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type VID[6] CMOS...
  • Page 43 Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 13. Pin Listing by Pin Name (Sheet 13 of 15) (Sheet 14 of 15) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Power/Other Power/Other...

  • Page 44: Pin Listing By Pin Number

    Package Mechanical Specifications and Pin Information Table 13. Pin Listing by Pin Name Table 14. Pin Listing by Pin Number (Sheet 15 of 15) (Sheet 2 of 17) Signal Signal Buffer Pin Name Direction Pin Name Direction Number Buffer Type Number Type THRMDA...
  • Page 45 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 3 of 17) (Sheet 4 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Open Drain...
  • Page 46 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 5 of 17) (Sheet 6 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type AD14...
  • Page 47 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 7 of 17) (Sheet 8 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type RSVD...
  • Page 48 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 9 of 17) (Sheet 10 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Input/...
  • Page 49 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 11 of 17) (Sheet 12 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Power/Other...
  • Page 50 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 13 of 17) (Sheet 14 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Input/...
  • Page 51 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number Table 14. Pin Listing by Pin Number (Sheet 15 of 17) (Sheet 16 of 17) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Input/...
  • Page 52 Package Mechanical Specifications and Pin Information Table 14. Pin Listing by Pin Number (Sheet 17 of 17) Signal Buffer Pin Name Direction Number Type Input/ D[32]# Source Synch Output Input/ D[42]# Source Synch Output Power/Other Input/ D[40]# Source Synch Output Input/ DSTBN[2]# Source Synch...

  • Page 53: Alphabetical Signals Reference

    In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel® Celeron® FSB. Input/ A[35:3]#...
  • Page 54 BSEL[2:0] Output synthesizer. All agents must operate at the same frequency. The Intel® Celeron® processor 500 series for platforms based on the Mobile Intel® 965 Express Chipset family operates at a 533-MHz system bus frequency (133-MHz BCLK[1:0] frequency). COMP[3:0] must be terminated on the system board using precision...
  • Page 55 Sleep state to the Deep Sleep state. In order to DPSLP# Input return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the Intel® ICH8M I/O controller. DPWR# is a control signal used by the chipset to reduce power on DPWR# Input the processor data bus input buffers.
  • Page 56 STPCLK# is not asserted, FERR#/PBE# assertion indicates that an unmasked floating point error has been detected. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service.
  • Page 57 APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous. LINT[1:0]...
  • Page 58 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 6 of 8) Name Type Description Probe Ready signal used by debug tools to determine processor debug readiness. PRDY# Output Please refer to the appropriate platform design guide for more implementation details.
  • Page 59 Package Mechanical Specifications and Pin Information Table 15. Signal Description (Sheet 7 of 8) Name Type Description SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
  • Page 60 V are voltage feedback signals to SS_SENSE CC_SENSE Intel MVP 6 that control the 2.1-mΩ loadline at the processor die. It Output SS_SENSE should be used to sense or measure ground near the silicon with little noise.

  • Page 61: Thermal Specifications

    As measured by the activation of the on-die Intel® Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 62: Thermal Diode

    Please contact your external sensor supplier for their recommendation. The thermal diode is separate from the Intel Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.

  • Page 63: Thermal Diode Ntrim And Diode Correction Toffset

    2, 3, 5 NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range.

  • Page 64: Intel® Thermal Monitor

    4.52 6.24 Ω 3, 6 NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Same as I Table Characterized across a temperature range of 50-100°C. Not 100% tested. Specified by design characterization. The ideality factor, n...
  • Page 65 Processor performance is decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC is activated immediately independent of the processor temperature.

  • Page 66: Digital Thermal Sensor

    Intel Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (C0 state).

  • Page 67: Prochot# Signal Pin

    If the Intel Thermal Monitor 1 is enabled (note that the Intel Thermal Monitor 1 must be enabled for the processor to be operating within specification), the TCC is active when PROCHOT# is asserted.

This manual is also suitable for:

Celeron 500 series

Table of Contents