Tables
1-1
1-2
Related Documents.................................................................................................21
2-1
2-2
2-3
Reference Clock......................................................................................................36
4-1
System States........................................................................................................45
4-2
4-3
4-4
PCIe Link States .....................................................................................................46
4-5
DMI States ............................................................................................................46
4-6
4-7
4-8
4-9
5-1
TDP Specifications ..................................................................................................67
5-2
5-3
5-4
6-1
6-2
Memory Channel A..................................................................................................78
6-3
Memory Channel B..................................................................................................79
6-4
6-5
6-6
6-7
6-8
6-9
6-10 PLL Signals ............................................................................................................82
6-11 TAP Signals............................................................................................................82
6-13 Power Sequencing ..................................................................................................83
6-15 Sense Pins.............................................................................................................84
6-16 Ground and NCTF ...................................................................................................85
7-1
7-2
7-3
Signal Groups1.......................................................................................................93
7-4
7-5
7-6
7-7
7-8
7-9
8
Datasheet, Volume 1
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