Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet page 44

• More efficient MSR interface to access APIC registers
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode.
• The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically,
the software semantics for using the Interrupt Command Register (ICR) and End Of
Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
The x2APIC extensions are made available to system software by enabling the local
x2APIC unit in the "x2APIC" mode. To benefit from x2APIC capabilities, a new
Operating System and a new BIOS are both needed, with special support for the
x2APIC mode.
The x2APIC architecture provides backward compatibility to the xAPIC architecture and
forward extendibility for future Intel platform innovations.
Note: Intel x2APIC technology may not be available on all processor SKUs.
For more information, refer to the Intel
http://www.intel.com/products/processor/manuals/
44
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64 Architecture x2APIC Specification at
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Technologies
Datasheet, Volume 1