Intel 2ND GENERATION CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 Datasheet page 19

Introduction
Execute Disable Bit
IMC
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Intel 64 Technology
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Intel DPST
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Intel FDI
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Intel TXT
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Intel Virtualization
Technology
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Intel VT-d
IOV
ITPM
LCD
LVDS
NCTF
PCH
PECI
PEG
Processor
Processor Core
Processor Graphics
Rank
SCI
Storage Conditions
TAC
TDP
Datasheet, Volume 1
Term
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
Developer's Manuals for more detailed information.
Integrated Memory Controller
64-bit memory extensions to the IA-32 architecture
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Intel Display Power Saving Technology
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Intel Flexible Display Interface
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Intel Trusted Execution Technology
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
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Intel Virtualization Technology (Intel
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
I/O Virtualization
Integrated Trusted Platform Module
Liquid Crystal Display
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
Non-Critical to Function. NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
Platform Environment Control Interface
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
The 64-bit, single-core or multi-core component (package).
The term "processor core" refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
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Intel Processor Graphics
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SO-
DIMM.
System Control Interrupt. Used in ACPI protocol.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air"
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Thermal Averaging Constant.
Thermal Design Power.
Description
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64 and IA-32 Architectures Software
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VT) for Directed I/O. Intel VT-d is a
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