Figure A.10. Power Regulators - Lattice Semiconductor MachXO3-940 User Manual

MachXO3-9400 Development Board
Evaluation Board User Guide
5
VBUS_5V
C86
0.1uF L3
D
600ohm 500mA
J11 USB_MINI_B DI
1 VBUS
VCC
2 D-
D-
3 D+
D+
4
NC
5
GND
6 SHLD C101
CASE
7 0.01uF
CASE
8
CASE
9 R164 100K
CASE
10
MH1
11
MH2
C
VBUS_5V
U8
R135 3
IN OUT
TAB
1K
D18 C88
GND
Blue
10uF
1
B
U9
3
Input Output
C96
Tab
A 10uF
TLV1117LV12DCY
DNI
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
4
R163 0
DM [3]
DP [3]
R162 0
VBUS_5V
D19
1 6
GND VBUS
DM 2 5 DM
NC2 D+
DP 3 4 DP
NC3 D-
ESDR0502N-UDFN6
R136 0 L4
3.3V_OUT
2 2
4
600ohm 500mA
C89 C90
22uF 0.1uF
NCP1117
3.3V_IN
+1.2V
R140 0 L5
1.2V_OUT 1.2V_IN
2 2 1
600ohm 500mA
4 C95
R141
22uF
100
4

Figure A.10. Power Regulators

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3
+3.3V VCCIO1
+3.3V VCCIO0
R125 1
R124 1
+1.2V
+1.2V
R129 1
DNI
+3.3V_AR
R128 1
DNI
R151 1
DNI
TP54 TP55
VCCIO0 VCCIO1
+3.3V VCCIO3 +3.3V VCCIO4
R132 1 R133 1
+3.3V
+1.2V +1.2V
1
R137 1 R138 1
DNI
DNI
+3.3V_RASP
TP58
R158 1
VCCIO4
DNI
TP57
VCCIO3
TP62 TP81
TP61
+1.2V
MH1 MH2 MH3
ThruHole ThruHole ThruHole
MH5 MH6 MH7
ThruHole ThruHole ThruHole
3
2
NOTE : Boot from external SPI Flash (U6)
requires VCCIO2 set to 3.3V.
when setting VCCIO2 to any other voltage.
+3.3V VCCIO2
[8] ASC_IMONN
R126 1
[8] ASC_IMONP
+1.2V
R269
+3.3V
0
R130 1 R123 1
DNI
+1.2V
VCC_CORE_P
R127 1
TP56
VCCIO2
DNI
TP53
VCC_CORE
+3.3V VCCIO5
+3.3V
R134 1
+1.2V
C91 C92 C93
R139 1 10uF 1uF 0.1uF
DNI
TP59 TP60
VCCIO5 +3.3V
TP82 TP83 TP84 TP85
J12 J13
GND GND
1 1
spread across board, easy access
MH4
ThruHole
Lattice Semiconductor Applications Lattice Semiconductor Applications Lattice Semiconductor Applications
MH8
http://www.latticesemi.com http://www.latticesemi.com http://www.latticesemi.com
ThruHole
Phone (503) 268-8001 -or- (800) LATTICE Phone (503) 268-8001 -or- (800) LATTICE Phone (503) 268-8001 -or- (800) LATTICE
Title Title Title
Power Regulators Power Regulators Power Regulators
Size Size Size Project Project Project
B B B MachXO3-9400-Dev-Brd MachXO3-9400-Dev-Brd MachXO3-9400-Dev-Brd
Date: Date: Date: Monday, May 22, 2017 Monday, May 22, 2017 Monday, May 22, 2017
2
1
Use caution
VCC_CORE D
R270
0
0.020
R181
C
C94
0.01uF
B
A
Schematic Rev Schematic Rev Schematic Rev 4.0 4.0 4.0
Board Rev Board Rev Board Rev
B B B
Sheet Sheet Sheet 10 10 10 of of of 10 10 10
1
FPGA-EB-02004-1.0