Intel Agilex F Series User Manual page 51

A. Development Kit Components
739942 | 2022.09.21
Schematic Signal Name FPGA Pin Number
DDR4_DIMM1_TDQS_N15
DDR4_DIMM1_DQ56
DDR4_DIMM1_DQ57
DDR4_DIMM1_DQ58
DDR4_DIMM1_DQ59
DDR4_DIMM1_DQ60
DDR4_DIMM1_DQ61
DDR4_DIMM1_DQ62
DDR4_DIMM1_DQ63
DDR4_DIMM1_DQS_P7
DDR4_DIMM1_DQS_N7
DDR4_DIMM1_DBI_N7
DDR4_DIMM1_TDQS_N16
DDR4_DIMM1_DQ64
DDR4_DIMM1_DQ65
DDR4_DIMM1_DQ66
DDR4_DIMM1_DQ67
DDR4_DIMM1_DQ68
DDR4_DIMM1_DQ69
DDR4_DIMM1_DQ70
DDR4_DIMM1_DQ71
DDR4_DIMM1_DQS_P8
DDR4_DIMM1_DQS_N8
DDR4_DIMM1_DBI_N8
DDR4_DIMM1_TDQS_N17
DDR4_DIMM1_C1
DDR4_DIMM1_C0
DDR4_DIMM1_BG0
DDR4_DIMM1_BA1
DDR4_DIMM1_BA0
DDR4_DIMM1_A17
DDR4_DIMM1_A16
Send Feedback
I/O Standard
DA23 1.2 V HS LVCMOS
CY12 1.2 V HS LVCMOS
DC13 1.2 V HS LVCMOS
DA13 1.2 V HS LVCMOS
DD12 1.2 V HS LVCMOS
DC9 1.2 V HS LVCMOS
DA9 1.2 V HS LVCMOS
CY8 1.2 V HS LVCMOS
DD8 1.2 V HS LVCMOS
DD10 1.2 V HS LVCMOS
DC11 1.2 V HS LVCMOS
CY10 1.2 V HS LVCMOS
DA11 1.2 V HS LVCMOS
CW23 1.2 V HS LVCMOS
CV22 1.2 V HS LVCMOS
CT22 1.2 V HS LVCMOS
CR23 1.2 V HS LVCMOS
CR19 1.2 V HS LVCMOS
CV18 1.2 V HS LVCMOS
CW19 1.2 V HS LVCMOS
CT18 1.2 V HS LVCMOS
CV20 1.2 V HS LVCMOS
CW21 1.2 V HS LVCMOS
CT20 1.2 V HS LVCMOS
CR21 1.2 V HS LVCMOS
CN29 1.2 V HS LVCMOS
CP28 1.2 V HS LVCMOS
CR25 1.2 V HS LVCMOS
CT24 1.2 V HS LVCMOS
CW25 1.2 V HS LVCMOS
CV24 1.2 V HS LVCMOS
CR27 1.2 V HS LVCMOS
Intel
DDR4 DIMM1 Termination Data Strobe for byte lane 6
DDR4 DIMM1 DQ56 data
DDR4 DIMM1 DQ57 data
DDR4 DIMM1 DQ58 data
DDR4 DIMM1 DQ59 data
DDR4 DIMM1 DQ60 data
DDR4 DIMM1 DQ61 data
DDR4 DIMM1 DQ62 data
DDR4 DIMM1 DQ63 data
DDR4 DIMM1 Data Strobe
Positive for byte lane 7
DDR4 DIMM1 Data Strobe
Negative for byte lane 7
DDR4 DIMM1 Data Bus Inversion for byte lane 7
DDR4 DIMM1 Termination Data Strobe for byte lane 7
DDR4 DIMM1 DQ64 data
DDR4 DIMM1 DQ65 data
DDR4 DIMM1 DQ66 data
DDR4 DIMM1 DQ67 data
DDR4 DIMM1 DQ68 data
DDR4 DIMM1 DQ69 data
DDR4 DIMM1 DQ70 data
DDR4 DIMM1 DQ71 data
DDR4 DIMM1 Data Strobe
Positive for byte lane 8
DDR4 DIMM1 Data Strobe
Negative for byte lane 8
DDR4 DIMM1 Data Bus Inversion for byte lane 8
DDR4 DIMM1 Termination Data Strobe for byte lane 8
DDR4 DIMM1 Stacked Device Chip ID 1
DDR4 DIMM1 Stacked Device Chip ID 0
DDR4 DIMM1 Bank Group 0
DDR4 DIMM1 Bank Address 1
DDR4 DIMM1 Bank Address 0
DDR4 DIMM1 Address 17
DDR4 DIMM1 Address 16
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Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
Description
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