Switch Description - Intel Agilex F Series User Manual

Figure 24. Switch and Jumper Locations
A.3.1. Switch Description
Table 17. SW1—4 Position DIP for PCIe Lane Width Selection
Switch position
1
2
3
4
Table 18. SW2—Single DIP for Intel FPGA Download Cable II Selection
Switch position
SW2 USB MAX JTAG SEL
Table 19. SW3—4 position DIP for Configuration Mode Selection and JTAG Control
By default,
Switch position
1
2
3
4
The board only supports the following configuration modes.
® ™
Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
38
J106 J105
Agilex
FPGA
Board Label
x16
x8
x4
x1
Board Label
ON for on-board Intel FPGA Download Cable II
OFF for external Intel FPGA Download Cable II
is set to '001' for AS x4 with CvP support.
MSEL[2:0]
Board Label
MSEL1
MSEL2
BMC JTAG SEL
HPS JTAG BYPASS
Top Side of Board
Function
ON for PCIe x16
ON for PCIe x8
ON for PCIe x4
ON for PCIe x1
Function
MSEL0
Function
Configuration MSEL1
Configuration MSEL2
ON Selects On-board Blaster
OFF Bypass HPS JTAG
A. Development Kit Components
739942 | 2022.09.21
SW5
SW2 SW6 S1 S2 S3 S4 S6
SW3
SW4
SW1
Default Position
ON
OFF
OFF
OFF
Default Position
ON
is tied to logic high.
Default Position
ON
ON
ON
OFF
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