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Board Reference
D5
Red over temperature LED
D12
Green FPGA CONF_DONE LED
D[11:D8]
4 green user LEDs
D[25:24]
2 green configuration image LEDs
Table 11.
Clock Circuits
Board
Reference
U23
ZL30733 IEEE 1588 clock device I
programmable by Intel MAX 10
U25, U26,
PCIe reference clocks
U27
•
U25: I
MAX 10 local
•
U26, U27: PCIe fan-out clock
buffers
Table 12.
Transceiver Interfaces
Board Reference
J1
PCIe x16 gold fingers
J7, B1
QSFPDD-56 pluggable optics interface
J8, B2
QSFP-56 pluggable optics interface
J9
PCIe x4 over CXL connector
Table 13.
Memory Devices
Board Reference
J4
J5
U15–U19
U3, U4
®
™
Intel
Agilex
F-Series FPGA (Two F-Tiles) Development Kit User Guide
34
Type
Type
2
C
2
C programmable by Intel
Type
Type
DDR4 DIMM1 connector
DDR4 DIMM2 connector
DDR4 components
2 x 2 Gbit QSPI flash
LED is on when the Intel MAX 10 detects an over-temperature
condition on the board.
LED is on when the FPGA is successfully configured.
FPGA connected LEDs for user designs.
Indicates which FPGA configuration image is loaded.
Description
Default frequencies:
•
Out 0: 100 MHz
•
Out 1: 125 MHz
•
Out 2: 166.25 MHz
•
Out 3: 166.25 MHz
•
Out 4: 166.25 MHz
•
Out 5: 156.25 MHz
•
Out 6: 156.25 MHz
•
Out 7: 250 MHz
•
Out 8: 184.32 MHz
•
Out 9: 153.6 MHz
Default frequencies:
•
U25:
— Out 0: Local 100 MHz PCIe to U26
— Out 1: Local 100 MHz PCIe to U27
— Out 2: 100 MHz CXL PCIe root port clock to CXL connector J9
•
U26:
— Out 0: 100 MHz PCIe Bank 13A, CH5
— Out 1: 100 MHz PCIe Bank 13A, CH2
•
U27:
— Out 0: 100 MHz PCIe Bank 12C, CH0
— Out 1: 100 MHz PCIe Bank 12C, CH1
PCIe TX/RX x16 interface from FPGA Bank 13A.
8 TX/RX channels from FPGA Bank 12C, Quad2 and Quad3.
4 TX/RX channels from FPGA Bank 12C, Quad1.
PCIe TX/RX x4 interface from FPGA Bank 12C, Quad0.
DDR4 x72 DIMM module installed by default.
No DDR4 DIMM module installed by default.
DDR4 x40 interface for HPS.
FPGA Avalon-ST x16 configuration flash memory.
A. Development Kit Components
739942 | 2022.09.21
Description
Description
Description
continued...
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