Hps Daughter Card - Intel Agilex F Series User Manual

Table 40. On-Board Oscillators Sources for the FPGA
Source Schematic Signal Name
U23 TOD_MASTER_CLK_125M_P/N
CLK_FPGA_100M_P/N
PTP_SAMPLE_CLK_250M_P/N
DDR4_DIMM1_REFCLK_P/N
DDR4_DIMM2_REFCLK_P/N
DDR4_COMP_REFCLK_P/N
QSFP_REFCLK_P/N
QSFPDD_REFCLK_P/N
CIPRI_HIGH_REFCLK_P/N
CIPRI_LOW_REFCLK_P/N
U27 REFCLK_CXL_CONN_P/N
REFCLK_CXL_EP_P/N
U26 REFCLK_PCIE_13A_CH2_P/N
REFCLK_PCIE_13A_CH5_P/N
U10 FPGA_OSC_CLK1
A.9. HPS Daughter Card
The development kit includes an Intel HPS daughter card that mounts to a Samtec 48-
pin connector (J6) and connects to the Intel Agilex HPS I/O 48 bank. The HPS
daughter card provides SoC port functionality to the development kit. These ports
include Ethernet, USB, UART, I
information, refer to the
® ™
Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
64
Frequency I/O Standard
125 Mhz Differential
100 Mhz LVDS
250 Mhz Differential
166.625 Mhz LVDS
166.625 Mhz LVDS
166.625 Mhz LVDS
156.25 Mhz Differential
156.25 Mhz Differential
184.32 Mhz Differential
153.6 Mhz Differential
100 Mhz HCSL
100 Mhz HCSL
100 Mhz HCSL
100 Mhz HCSL
125 Mhz 1.8 V LVCMOS
2
C, JTAG, and a SD memory card slot. For more
HPS IO-48 OOBE Daughter
A. Development Kit Components
739942 | 2022.09.21
Intel Agilex Pin Application
Number (P/N)
G43/F44 IEEE 1588 TOD master clock
CK18/CL19 General-purpose FPGA clock
E45/D46 IEEE 1588 PTP clock
CV28/CW29 DDR4 DIMM1 clock
DD36/DC37 DDR4 DIMM2 clock
U5/T6 DDR4 component clock
AW49/AV48 QSFP clock
AD48/AC49 QSFPDD clock
AJ48/AH49 CIPRI high clock
AR49/AU49 CIPRI low clock
BG49/BF48 PCIe REFCLK bank 12C
channel 1
BC49/BE49 PCIe REFCLK bank 12C
channel 0
BR7/BU7 PCIe REFCLK bank 13A
channel 2
CD8/CC7 PCIe REFCLK bank 13A
channel 5
CB42 Configuration clock
Card.
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