Intel Agilex F Series User Manual page 33

A. Development Kit Components
739942 | 2022.09.21
Board Reference
U5
Table 9. Configuration and Setup Elements
Board
Reference
J10 On-board Intel FPGA Download
Cable II
SW1 PCIe control DIP switch
SW2 Intel FPGA Download Cable II
selection switch
SW3 JTAG bypass DIP switch
Position 1-2
SW3 Position MSEL configuration DIP switch
3-4
SW4 PCIe clock control DIP switch
SW5 Power-on slide switch
SW6 Intel MAX 10 JTAGEN switch
S1 CPU RESETn
S2 HPS RESETn
S3 1st_PCIe_PERSTN push-button
S4 2nd_PCIe_PERSTN push-button
S6 CXL_PCIe_PERSTN push-button
J105 Configuration image selection
J106 Configuration image selection
Table 10. Status Elements
Board Reference
D1 Green Intel MAX 10 CONF_DONE
LED
D2 Blue power good LED
Send Feedback
Type
• 32 x 32 Gbps Transceivers
• 24 x 58Gbps Transceivers
• 2340 pin BGA Package
CPLD Intel MAX 10 CPLD, 10M50DAF256I7G
Type
Micro-USB 2.0 connector for programming and debugging the
FPGA.
Enables PCIe link widths x1, x4, x8, and x16.
Selects between the on-board Intel FPGA Download Cable II or
external Intel FPGA Download Cable II connected to J3 header.
Enables and disables devices in the JTAG chain.
Sets the Intel Agilex MSEL configuration modes
Provides control for PCIe clock controls such as Spread Spectrum
enable/disable, local or external PCIe clock source, and PCIe
REFCLK power down.
Main switch for powering on the Board when used in bench-top
mode. This switch is ignored when the board is used in a PCIe
system.
Enables Intel MAX 10 to use the JTAG pins as I/Os.
Sends an active low signal to the FPGA and Intel MAX 10 which can
be used as the RESET for internal designs.
Sends an active low signal to the Intel MAX 10. Intel MAX 10 can
then send HPS_DC_RSTn to the HPS IO48 daughter card is
present.
Sends an active low signal to the dedicated PCIe_PERSTN pin of
transceiver Bank 13A.
Sends an active low signal to a GPIO pin in Bank 3A. This pin can
be used as a secondary PERSTN signal.
Sends an active low signal to the CXL connector PERSTN pin.
Use together with J106 to select image stored in U4 for Avalon-ST
x16.
Use together with J105 to select image stored in U4 for Avalon-ST
x16.
Type
LED is on when the Intel MAX 10 is successfully configured.
LED is on when Intel MAX 10 detects that all power on the board
is good.
®
Intel Agilex
Description
Description
Description
™
F-Series FPGA (Two F-Tiles) Development Kit User Guide
continued...
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