Custom Projects For The Development Kit; Add Smartvid Settings In The Intel Quartus Prime Qsf File; Golden Top - Intel Agilex F Series User Manual

Fpga (two f-tiles) development kit
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739942 | 2022.09.21
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6. Custom Projects for the Development Kit

6.1. Add SmartVID Settings in the Intel Quartus Prime QSF File

By default, the Intel Agilex silicon assembled on this development kit enables the
SmartVID feature. To avoid the Intel Quartus Prime software from generating an error
due to incomplete SmartVID settings, you must put constraints outlined below into the
Intel Quartus Prime project QSF file.
Open your Intel Quartus Prime project QSF file, copy and paste the following
constraint scripts into the file. Ensure there are no other similar settings with different
values.
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 55
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD 0
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name USE_INIT_DONE SDM_IO13
set_global_assignment -name USE_CVP_CONFDONE SDM_IO14
set_global_assignment -name USE_NCATTRIP SDM_IO12
set_global_assignment -name USE_HPS_COLD_RESET SDM_IO10

6.2. Golden Top

You can use the Golden Top project as the starting point for your designs. It comes
loaded with constraints, pin locations, defined I/O standard, direction, and general
termination.
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