The Sys Info Tab - Intel Agilex F Series User Manual

4. Board Test System
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Figure 8. The Configure Menu
To configure the FPGA with a test system design, follow these steps:
1. On the Configure menu, click the Configure command that corresponds to the
functionality you want to test.
2. In the dialog box that appears, click Configure to download the corresponding
design's SRAM Object File (.sof) to the FPGA. The download process usually takes
less than a minute.
3. When configuration finishes, the design begins running in the FPGA. The
corresponding GUI application tabs that interface with the design are now
enabled. If you use the Intel Quartus Prime Programmer for configuration, instead
of the BTS GUI, you need to restart the GUI.

4.2.3. The Sys Info Tab

The Sys Info tab shows information about the board's current configuration. The tab
displays the board information, JTAG Chain devices and other details stored on the
board.
Figure 9. The Sys Info Tab
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Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
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