Qsfp-Dd Interface - Intel Agilex F Series User Manual

Edge Finger pin Number
A40
A44
A48
A53
A57
A61
A65
A69
A73
A77
A81
A16
A21
A25
A29
A35
A39
A43
A47
A52
A56
A60
A64
A68
A72
A76
A80
B11
B12
A.5.2. QSFP-DD Interface
The Intel Agilex FPGA (two F-tiles) development board includes a connector and cages
system for mounting a Double Density Quad Small Form-Factor Pluggable (QSFP-DD)
module. The interface connects to eight 56 Gbps PAM4 capable F-tile lanes of the Intel
Agilex FPGA, supporting QSFP-DD modules, with capability of 400 Gbps aggregate
bandwidth with power classifications up to 10 W.
® ™
Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
44
Schematic Signal Name
PCIE_EP_RX_N5
PCIE_EP_RX_N6
PCIE_EP_RX_N7
PCIE_EP_RX_N8
PCIE_EP_RX_N9
PCIE_EP_RX_N10
PCIE_EP_RX_N11
PCIE_EP_RX_N12
PCIE_EP_RX_N13
PCIE_EP_RX_N14
PCIE_EP_RX_N15
PCIE_EP_RX_P0
PCIE_EP_RX_P1
PCIE_EP_RX_P2
PCIE_EP_RX_P3
PCIE_EP_RX_P4
PCIE_EP_RX_P5
PCIE_EP_RX_P6
PCIE_EP_RX_P7
PCIE_EP_RX_P8
PCIE_EP_RX_P9
PCIE_EP_RX_P10
PCIE_EP_RX_p11
PCIE_EP_RX_P12
PCIE_EP_RX_P13
PCIE_EP_RX_P14
PCIE_EP_RX_P15
PCIE_3V3_EP_WAKE
PCIE_3V3_EP_CLKREQn
FPGA Pin Number I/O Standard
AY8 1.4 V PCML
BC5 1.4 V PCML
BG5 1.4 V PCML
BL5 1.4 V PCML
BR5 1.4 V PCML
BW5 1.4 V PCML
CC5 1.4 V PCML
CG5 1.4 V PCML
CL5 1.4 V PCML
CM8 1.4 V PCML
CT8 1.4 V PCML
AK4 1.4 V PCML
AN7 1.4 V PCML
AP4 1.4 V PCML
AU7 1.4 V PCML
AV4 1.4 V PCML
BA7 1.4 V PCML
BB4 1.4 V PCML
BF4 1.4 V PCML
BK4 1.4 V PCML
BP4 1.4 V PCML
BV4 1.4 V PCML
CB4 1.4 V PCML
CF4 1.4 V PCML
CK4 1.4 V PCML
CN7 1.4 V PCML
CU7 1.4 V PCML
— 3.3V
— 3.3V
A. Development Kit Components
739942 | 2022.09.21
Description
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Wake Signal
Clock Request
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