Intel Agilex F Series User Manual page 49

A. Development Kit Components
739942 | 2022.09.21
Schematic Signal Name FPGA Pin Number
DDR4_DIMM1_DBI_N1
DDR4_DIMM1_TDQS_N10
DDR4_DIMM1_DQ16
DDR4_DIMM1_DQ17
DDR4_DIMM1_DQ18
DDR4_DIMM1_DQ19
DDR4_DIMM1_DQ20
DDR4_DIMM1_DQ21
DDR4_DIMM1_DQ22
DDR4_DIMM1_DQ23
DDR4_DIMM1_DQS_P2
DDR4_DIMM1_DQS_N2
DDR4_DIMM1_DBI_N2
DDR4_DIMM1_TDQS_N11
DDR4_DIMM1_DQ24
DDR4_DIMM1_DQ25
DDR4_DIMM1_DQ26
DDR4_DIMM1_DQ27
DDR4_DIMM1_DQ28
DDR4_DIMM1_DQ29
DDR4_DIMM1_DQ30
DDR4_DIMM1_DQ31
DDR4_DIMM1_DQS_P3
DDR4_DIMM1_DQS_N3
DDR4_DIMM1_DBI_N3
DDR4_DIMM1_TDQS_N12
DDR4_DIMM1_DQ32
DDR4_DIMM1_DQ33
DDR4_DIMM1_DQ34
DDR4_DIMM1_DQ35
DDR4_DIMM1_DQ36
Send Feedback
I/O Standard
DF18 1.2 V HS LVCMOS
DE19 1.2 V HS LVCMOS
DF8 1.2 V HS LVCMOS
DH8 1.2 V HS LVCMOS
DE9 1.2 V HS LVCMOS
DJ9 1.2 V HS LVCMOS
DF2 1.2 V HS LVCMOS
DE3 1.2 V HS LVCMOS
DF4 1.2 V HS LVCMOS
DE5 1.2 V HS LVCMOS
DH6 1.2 V HS LVCMOS
DJ7 1.2 V HS LVCMOS
DF6 1.2 V HS LVCMOS
DE7 1.2 V HS LVCMOS
DE15 1.2 V HS LVCMOS
DF14 1.2 V HS LVCMOS
DJ15 1.2 V HS LVCMOS
DH14 1.2 V HS LVCMOS
DF10 1.2 V HS LVCMOS
DH10 1.2 V HS LVCMOS
DJ11 1.2 V HS LVCMOS
DE11 1.2 V HS LVCMOS
DH12 1.2 V HS LVCMOS
DJ13 1.2 V HS LVCMOS
DF12 1.2 V HS LVCMOS
DE13 1.2 V HS LVCMOS
DH26 1.2 V HS LVCMOS
DE27 1.2 V HS LVCMOS
DF26 1.2 V HS LVCMOS
DJ27 1.2 V HS LVCMOS
DE23 1.2 V HS LVCMOS
Intel
Negative for byte lane 1
DDR4 DIMM1 Data Bus Inversion for byte lane 1
DDR4 DIMM1 Termination Data Strobe for byte lane 1
DDR4 DIMM1 DQ16 data
DDR4 DIMM1 DQ17 data
DDR4 DIMM1 DQ18 data
DDR4 DIMM1 D19 data
DDR4 DIMM1 DQ20 data
DDR4 DIMM1 DQ21 data
DDR4 DIMM1 DQ22 data
DDR4 DIMM1 DQ23 data
DDR4 DIMM1 Data Strobe
Positive for byte lane 2
DDR4 DIMM1 Data Strobe
Negative for byte lane 2
DDR4 DIMM1 Data Bus Inversion for byte lane 2
DDR4 DIMM1 Termination Data Strobe for byte lane 2
DDR4 DIMM1 DQ24 data
DDR4 DIMM1 DQ25 data
DDR4 DIMM1 DQ26 data
DDR4 DIMM1 DQ27 data
DDR4 DIMM1 DQ28 data
DDR4 DIMM1 DQ29 data
DDR4 DIMM1 DQ30 data
DDR4 DIMM1 DQ31 data
DDR4 DIMM1 Data Strobe
Positive for byte lane 3
DDR4 DIMM1 Data Strobe
Negative for byte lane 3
DDR4 DIMM1 Data Bus Inversion for byte lane 3
DDR4 DIMM1 Termination Data Strobe for byte lane 3
DDR4 DIMM1 DQ32 data
DDR4 DIMM1 DQ33 data
DDR4 DIMM1 DQ34 data
DDR4 DIMM1 DQ35 data
DDR4 DIMM1 DQ36 data
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Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
Description
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