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2
Figure 25.
I
C Block Diagram
QSFPDD
(S)
(J7)
ModSelL
QSFD
(S)
(J8)
ModSelL
HPS IO48
(J6)
Table 37.
Intel MAX 10 I
Schematic Signal Name
MAX_I2C_SCL
MAX_I2C_SDA
FX2_SCL
FX2_SDA
2
Table 38.
FPGA I
Schematic Signal Name FPGA Pin Number
FPGA_1V8_SVID_SCL
FPGA_1V8_SVID_SDA
FPGA_1V2_SCL
FPGA_1V2_SDA
HPS_SCL
HPS_SDA
®
™
Intel
Agilex
F-Series FPGA (Two F-Tiles) Development Kit User Guide
62
USB
FX2_SCL/SDA
Blaster
(M)
PHY
(U49)
DIMM1
DIMM2
ADDR=A0h
ADDR=A1h
(J4)
(J5)
ADDR=4 Eh
FPGA_SCL/SDA
(M)
(M)
Agilex FPGA
(M)
(U8)
HPS_SCL/SDA
(M)
(M)
(M)
FPGA SVID to VCC Regulator
M24128
FRUID
(S)
(U2)
ADDR=A0h
(M)
PCIe
Gold Finger
(J1)
2
C Signals
MAX Pin Number
J11
J12
R1
R3
C Signals
I/O Standard
CG47
1.8 V open drain
CB46
1.8 V open drain
K44
1.2 V open drain
J43
1.2 V open drain
N3
1.8 V open drain
L6
1.8 V open drain
LTC3888-1
SPI Bus
VCC,
VCC HSSI
(S)
MAX 10
(U61)
System Controller
(U5)
MAX_12C_SCL/SDA
(M)
ADDR=42h
MAX16545B
PCIe HSC
(U50)
IOEXP
ADDR=56h/5 Eh
(U97)
ADDR=40h
M24128
CERT
MAX16545B
(S)
EEPROM
AUX HSC
(U46)
(U54)
IO48
Daughter
(S)
Card
I/O Standard
3.3 V open drain
3.3 V open drain
3.3 V open drain
3.3 V open drain
Serial voltage ID I
Serial voltage ID I
2
FPGA I
C clock for DDR4 DIMMs, QSFP, QSFPDD, IO
expander, and certificate EEPROM
2
FPGA I
C data for DDR4 DIMMs, QSFP, QSFPDD, IO
expander, and certificate EEPROM
HPS I/O48 daughter card I
HPS I/O48 daughter card I
A. Development Kit Components
739942 | 2022.09.21
ADDR=55h
(S)
(S)
ZL30733
(S)
Clock
(U23)
(S)
Si52204
(S)
Clock
(U25)
M24128
(S)
MAC
(S)
EEPROM
(U44)
LTC7132
VCCERT_FGT_GXF
(S)
VCCR_CORE
(U93)
LTC7132
VCCPT
(S)
VCCIO_1V2
(U96)
MAX31730
Temp Sense
(EU1)
MAX31730
Temp Sense
(EU2)
Description
2
Intel MAX 10 I
C clock
2
Intel MAX 10 I
C data
2
USB PHY I
C clock
2
USB PHY I
C data
Description
2
C clock
2
C data
2
C clock
2
C data
Send Feedback
ADDR=70h
ADDR=6Ah
ADDR=57h/5Fh
ADDR=74h
ADDR=75h
ADDR=38h
ADDR=9Ah
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