Feature Summary - Intel Agilex F Series User Manual

1. Overview
739942 | 2022.09.21

1.2. Feature Summary

• Intel Agilex F-Series (AGFB027) device in 2340A BGA package
— Quad-core 64-bit Arm Cortex-A53 hard processor (HPS)
— 0.8 V VID-adjustable VCC core
— Dual F-tile transceivers supporting 56 Gbps (PAM4) and 32 Gbps (NRZ) data
rates
— 2.69M logic elements (LE)
— 3.65M adaptive logic modules (ALM)
— 8.5K digital signal processing (DSP) blocks
• FPGA configuration
— Avalon
— 2 Gb flash for AS x4
— Dual 2 Gb flash for Avalon-ST x16
— JTAG header for device programming
— Built-in Intel FPGA Download Cable II for device programming
• Programmable clock sources
• Transceiver interfaces
— PCI Express* (PCIe) x16 interface supporting Gen 4 end-point connected to a
PCIe x16 edge connector (gold edge fingers)
— 1x QSFP optical module interface connected to F-tile transceiver
— 1x QSFPDD optical module interface connected to F-tile transceiver
— 1x PCIe/CXL interface supporting x4 interface connected to MCIO connector
• Memory interfaces
— Two x72 DIMM sockets supporting DDR4-2666 or DDR-T Intel Optane
persistent memory module
— Single x40 DDR4 component interface for HPS processor memory
• Communication ports
— JTAG header
— Micro USB on-board Intel FPGA Download Cable II
— System I2C header
• Buttons, switches, and LEDs
— CPU reset push button
— PCIe reset push button
— CXL reset push button
— HPS reset push button
— Four dedicated user LEDs
— Board power good LED
— FPGA configuration done LED
Send Feedback
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-ST x16 and active serial (AS) x4 configuration modes support
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Intel Agilex
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F-Series FPGA (Two F-Tiles) Development Kit User Guide
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