Intel Agilex F Series User Manual page 42

The PCI Express interface supports auto-negotiating channel width from x1 to x4 to x8
to x16 by using PCIe Intel FPGA IP. You can also configure this board to a x1, x4, x8,
or x16 interface through a DIP switch that connects the
width.
The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a
maximum of 40 Gbps full-duplex (Gen 1), 5.0 Gbps/lane for maximum of 80 Gbps full-
duplex (Gen 2), or 8.0 Gbps/lane for a maximum of 128 Gbps full-duplex (Gen 3), and
16.0 Gbps/lane for a maximum of 256 Gbps full-duplex (Gen 4).
The power for the board can be sourced entirely from the PC host when installed into
a PC motherboard with the PC's 2x4 ATX auxiliary power connected to the 12V ATX
inputs (J11) of the Intel Agilex FPGA (two F-tiles) development board. Although the
board can also be powered by an externally supplied power supply for use on a lab
bench, Intel recommends that you do not power up from both supplies at the same
time. Ideal diode power sharing devices have been designed into this board to prevent
damages or backcurrent from one supply to the other.
The
REFCLK_PCIE_EP_EDGE_P/N
from the PC motherboard onto this board through the edge connector. This signal
connects directly to a Intel Agilex FPGA
clock is terminated on the motherboard. Therefore, no on-board termination is
required. This clock can have spread-spectrum properties that change its period
between 9.847 ps to 10.203 ps. The I/O standard is high-speed current steering logic
(HCSL).
Table 29. PCI Express (PCIe) Pin Assignments
Edge Finger pin Number
A11
A14
A13
B5
B6
A1
B17
B31
B48
B81
B15
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Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit User Guide
42
Schematic Signal Name
PCIE_3V3_EP_PERSTN
REFCLK_PCIE_EP_EDGE_N
REFCLK_PCIE_EP_EDGE_P
PCIE_3V3_EP_SMBCLK
PCIE_3V3_EP_SMBDAT
PCIE_EP_PRSNT_N
PCIE_EP_PRSNT_Nx1
PCIE_EP_PRSNT_Nx4
PCIE_EP_PRSNT_Nx8
PCIE_EP_PRSNT_Nx16
PCIE_EP_TX_N0
PRSTn
signal is a 100 MHz differential input that is driven
input pin pair using DC coupling. This
REFCLK
FPGA Pin Number I/O Standard
MAX10 (U5) 3V LVCMOS
Clock Buffer (U26) LVDS
Clock Buffer (U26) LVDS
FRUID EEPROM (U2) 1.8V
FRUID EEPROM (U2) 1.8V
— —
— —
— —
— —
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AG5 1.4 V PCML
A. Development Kit Components
739942 | 2022.09.21
pins for each bus
Description
Reset
Motherboard reference
clock
Motherboard reference
clock
SMB clock
SMB data
Link with DIP switch
(SW1)
Link with DIP switch
(SW1)
Link with DIP switch
(SW1)
Link with DIP switch
(SW1)
Link with DIP switch
(SW1)
Receive bus
continued...
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