Table of Contents
Advertisement
A. Development Kit Components
739942 | 2022.09.21
Edge Finger pin Number
B20
B24
B28
B34
B38
B42
B46
B51
B55
B59
B63
B67
B71
B75
B79
B14
B19
B23
B27
B33
B37
B41
B45
B50
B54
B58
B62
B66
B70
B74
B78
A17
A22
A26
A30
A36
Send Feedback
Schematic Signal Name
PCIE_EP_TX_N1
PCIE_EP_TX_N2
PCIE_EP_TX_N3
PCIE_EP_TX_N4
PCIE_EP_TX_N5
PCIE_EP_TX_N6
PCIE_EP_TX_N7
PCIE_EP_TX_N8
PCIE_EP_TX_N9
PCIE_EP_TX_N10
PCIE_EP_TX_N11
PCIE_EP_TX_N12
PCIE_EP_TX_N13
PCIE_EP_TX_N14
PCIE_EP_TX_N5
PCIE_EP_TX_P0
PCIE_EP_TX_P1
PCIE_EP_TX_P2
PCIE_EP_TX_P3
PCIE_EP_TX_P4
PCIE_EP_TX_P5
PCIE_EP_TX_P6
PCIE_EP_TX_P7
PCIE_EP_TX_P8
PCIE_EP_TX_P9
PCIE_EP_TX_P10
PCIE_EP_TX_P11
PCIE_EP_TX_P12
PCIE_EP_TX_P13
PCIE_EP_TX_P14
PCIE_EP_TX_P15
PCIE_EP_RX_N0
PCIE_EP_RX_N1
PCIE_EP_RX_N2
PCIE_EP_RX_N3
PCIE_EP_RX_N4
Intel
FPGA Pin Number
I/O Standard
AH2
1.4 V PCML
AM2
1.4 V PCML
AT2
1.4 V PCML
AY2
1.4 V PCML
BD2
1.4 V PCML
BH2
1.4 V PCML
BM2
1.4 V PCML
BT2
1.4 V PCML
BY2
1.4 V PCML
CD2
1.4 V PCML
CH2
1.4 V PCML
CM2
1.4 V PCML
CR5
1.4 V PCML
CT2
1.4 V PCML
CW5
1.4 V PCML
AF4
1.4 V PCML
AJ1
1.4 V PCML
AN1
1.4 V PCML
AU1
1.4 V PCML
BA1
1.4 V PCML
BE1
1.4 V PCML
BJ1
1.4 V PCML
BN1
1.4 V PCML
BU1
1.4 V PCML
CA1
1.4 V PCML
CE1
1.4 V PCML
CJ1
1.4 V PCML
CN1
1.4 V PCML
CP4
1.4 V PCML
CU1
1.4 V PCML
CV4
1.4 V PCML
AL5
1.4 V PCML
AM8
1.4 V PCML
AR5
1.4 V PCML
AT8
1.4 V PCML
AW5
1.4 V PCML
®
™
Agilex
F-Series FPGA (Two F-Tiles) Development Kit User Guide
Description
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Receive bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
Transmit bus
continued...
43
Advertisement
Table of Contents
