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11 1 A D Conversion Process
The conversion process is initiated by the execution of
HSO command 0FH or by writing a one to the GO Bit
in the A D Control Register Either activity causes a
start conversion signal to be sent to the A D converter
control logic If an HSO command was used the con-
version process will begin when Timer1 increments
This aids applications attempting to approach spectral-
ly pure sampling since successive samples spaced by
equal Timer1 delays will occur with a variance of about
50 ns (assuming a stable clock on XTAL1) Howev-
g
er conversions initiated by writing a one to the AD-
CON register GO Bit will start within three state times
after the instruction has completed execution resulting
in a variance of about 0 50 ms (XTAL1
Once the A D unit receives a start conversion signal
there is a one state time delay before sampling (Sample
Delay) while the successive approximation register is
reset and the proper multiplexer channel is selected
After the sample delay the multiplexer output is con-
nected to the sample capacitor and remains connected
for 8 state times in fast mode or 15 state times for slow
mode (Sample Time) After this 8 15 state time ''sam-
ple window'' closes the input to the sample capacitor is
disconnected from the multiplexer so that changes on
the input pin will not alter the stored charge while the
conversion is in progress The comparator is then auto-
zeroed and the conversion begins The sample delay
and sample time uncertainties are each approximately
50 ns independent of clock speed
g
To perform the actual analog-to-digital conversion the
80C196KB implements a successive approximation al-
gorithm The converter hardware consists of a 256-re-
sistor ladder a comparator coupling capacitors and a
10-bit successive approximation register (SAR) with
logic that guides the process The resistor ladder pro-
vides 20 mV steps (V
REF
coupling creates 5 mV steps within the 20 mV ladder
voltages Therefore 1024 internal reference voltages are
available for comparison against the analog input to
generate a 10-bit conversion result
A successive approximation conversion is performed by
comparing a sequence of reference voltages to the ana-
log input in a binary search for the reference voltage
that most closely matches the input The
reference voltage is the first tested This corresponds to
a 10-bit result where the most significant bit is zero
and all other bits are ones (0111 1111 11b) If the ana-
log input was less than the test voltage bit 10 of the
SAR is left a zero and a new test voltage of
(0011 1111 11b) is tried If this test voltage was lower
than the analog input bit 9 of the SAR is set and bit 8
is cleared for the next test (0101 1111 11b) This binary
search continues until 10 tests have occurred at which
time the valid 10-bit conversion result resides in the
SAR where it can be read by software
12 MHz)
e
5 12V) while capacitive
e
full scale
full scale
80C196KB USER'S GUIDE
The total number of state times required for a conver-
sion is determined by the setting of IOC2 4 clock pre-
scaler bit With the bit set the conversion time is 91
states and 158 states when the bit is cleared
11 2 A D Interface Suggestions
The external interface circuitry to an analog input is
highly dependent upon the application and can impact
converter characteristics In the external circuit's de-
sign important factors such as input pin leakage sam-
ple capacitor size and multiplexer series resistance from
the input pin to the sample capacitor must be consid-
ered
For the 80C196KB these factors are idealized in Fig-
ure 11-5 The external input circuit must be able to
charge a sample capacitor (C
ance (R
) to an accurate voltage given a D C leakage
I
(I
) On the 80C196KB C
L
around 5 KX and I
is specified as 3 mA maximum In
L
determining the necessary source impedance R
value of V
is not important
BIAS
Figure 11-5 Idealized A D Sampling Circuitry
External circuits with source impedances of 1 KX or
less will be able to maintain an input voltage within a
tolerance of about
0 61 LSB (1 0 KX
g
3 0 mV) given the D C leakage Source impedances
above 2 KX can result in an external error of at least
one LSB due to the voltage drop caused by the 3 mA
leakage In addition source impedances above 25 KX
may degrade converter accuracy as a result of the inter-
nal sample capacitor not being fully charged during the
1 ms (12 MHz clock) sample window
If large source impedances degrade converter accuracy
because the sample capacitor is not charged during the
sample time an external capacitor connected to the pin
compensates for this Since the sample capacitor is
2 pF a 0 005 mF capacitor (2048
the sample capacitor to an accurate input voltage of
0 5 LSB An external capacitor does not compensate
g
for the voltage drop across the source resistance but
charges the sample capacitor fully during the sample
time
) through a series resist-
S
is around 2 pF R
is
S
I
the
S
270651 –35
3 0 mA
e
c
2 pF) will charge
53
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