Agilent Technologies PSA Series Service Manual page 219

Spectrum analyzer
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E4446A/E4447A/E4448A OVERALL BLOCK DIAGRAM
A19
A19 FL1
27 GHz LPF
A14 INPUT ATTENUATOR A
Cable
SBTX
-35dBm
@ 50MHz
-25 dBm
W7
3 Hz - 26.8 GHz
-38dBm
@ 5GHz
RF-INPUT
DC COUPLED
> 26.8 GHz
3 Hz to fmax
Preselector
W20
SBTX LB
A
Switch
6 dB
2 dB
2 dB
Calibrator Signal
50 MHz CW, -25 dBm
LO1
W29
50W
W68
fmax: E4446A = 44 GHz
W34
E4447A = 42.98 GHz
A15 INPUT ATTENUATOR B
20
E4448A = 50 MHz
W8
A29
LOMA/SBTX Driver
10 dB
30 dB
20 dB
W33
J1
J9
24
14
J2
J10
W30
20
10
10
W69
W47
PRE-SEL OUT
W70
(REAR PANEL)
J5
J6
J14
J4
J3
J11
A13 FRONT END DRIVER
10 kHz
ELECTRONIC
J13
W53
ATTENUATOR
10 Mhz
ATTENUATOR
16
CONTROL
REF.
CONTROL
1/N
1/N
COUNTER
BIT
W71
DAC
N=1-2
N=1-2
32
32
UNPRESELECTED
YTO
J7
W25
MIXER CONTROL
MAIN COIL
DELAY
BIAS/CTRL
FM COIL
A18
10
COMP.
PASS THRU
YTF TUNE RAMP GENERATOR
THERMOMETER
FROM LO VIA
10 kHz
N=1-2
48
MOTHERBOARD
16
COUNTER
BIT
1/N
TO 3rd CONVERTER
DAC
VIA MOTHERBOARD
+32v
VARIABLE GAIN RAMP GENERATOR
FIFA
LOWBAND
MODULE
28v
PREAMP
REGULATOR
BIAS/CONTROL
BIAS/CTRL
BIAS/CTRL
J8
J9
J10
W49
W58
TO REAR PANEL
W31
B
F
20
20
28v (SWITCHED)
A12 LO SYNTHESIZER
J1
A12 A1 SYNTHESIZER
3-7 GHz
A12 A2 SAMPLING OSCILLATOR DAUGHTER BD.
614-718 MHz
N*600/256+600MHz
J1
J3
F
S
DUAL PATH LOOP
¦
A12W1
SINGLE
SAMPLER IF
LOOP
OFFSET SAMPLING
PATH
OSC. PLL
90 MHz
R
LPF
1/8
375-875 MHz
RATE
L
MULTIPLIER
NARROW SPAN
WIDE SPAN
N=6-63
50-70 MHz
(DUAL LOOP)
(SINGLE LOOP)
J3
TESSERA
MODULUS
J4
A12W2
1200MHz
CONTROL
NARROW SPAN
X2
PAREN
PRETUNE GAIN
WIDE SPAN
R=5, 6, 7 (DUAL LOOP)
129 (SINGLE LOOP)
CONTROL
F
1/R
(600 MHz FROM MOTHERBOARD)
¦
sn51a
A27 ELECTRONIC ATTENUATOR
- 36 dBm
OPTION B7J
RYTHM
3 Hz - 2.85 GHz
W52
LOW BAND
YTF
W51
0-40 dB IN 1dB STEPS
Odd/Even IF
FL1
3 GHz, LPF
W17
2.85 - 26.8 GHz
HIGH BAND
W48
LO 3-7 GHz
MM BAND
3.92 GHz
A22 LOWBAND PREAMP
-48 dBm
OPTION 1DS
+30 dBm
W38
Coax
Switch
A30 FIFA
W55
W49
3.9214 GHz
+17
-32 dBm
B
W56
F
CF= 3.9214 GHz
BW= 40MHz
2 dB
W54
W42
AT1
W43
A20 LOWBAND
A21 FREQ. EXT. LO MULTIPLIER/AMP (FELOMA)
(5087-7126)
FIRST MIXER
W50
3Hz-3GHz
J2
X2
+13 dBm
J1
6-14 GHz
-36 dBm
W35
J1
J3
+14 dBm
+12
SW1
LIMITER
3-7 GHz YTO
50
W41
1ST LO
LO
J4
3-7 GHz
J2
BIAS-ADJ.
+ 14 dBm
U1
J5
J6
W46
W45
Front Panel
3-7 GHz
W24
(1st LO Output 3-7 GHz
-9 dBm
+ 15 dBm Nominal)
(Option AYZ)
J8
26
PRETUNE
A11 REFERENCE BOARD
GENERATOR
100 MHz PLL
UNLOCK DETECTOR
W22
DAC
(70)
100 MHz
P1
VCO
¦
REAR PANEL
1/R
F
EXT. REF INPUT
LOOP GAIN
1MHz TO 30MHz
DELAY
1/F,N
COMP
PAREN
1 / 2
FRAC-N
MODULUS
CONTROL
MAIN COIL
FILTER
REAR PANEL
1 / 5
TO FE
10MHz REF OUT
EXT. REF OUT OFF
MAIN COIL
DRIVER
+5dBm
P2
VIA
FM COIL
MOTHERBOARD.
W21
(90)
A10 THIRD CONVERTER
EXT. MIXER BIAS
W44
J3
Front Panel
BIAS T
IF IN
(321.4 MHz Nominal
-20 dBm, Max)
W17
(Option AYZ)
0-30 dB
(10)
2 dB/STEP
14dB
J1
321.4 MHz
-50 dBm
14dB
321.4 MHz
J2
-44 dBm
-.5 TO
3 V
VARIABLE GAIN
RAMP FROM FE
FL2
DRIVER VIA MOTHERBOARD
BPF
50 MHz CALIBRATOR ALC
50 MHz
FROM
W39
REFERENCE
BOARD VIA
MOTHERBOARD
3.9214 GHz
-30 dBm
-33 dBm
OVERLOAD
J3
J4
DETECTOR
3dB
2dB
SECOND
MIXER
400 MHz
W18
THERMOMETER
9dB
(7)
J7
1ST IF AMP
RING RESONATOR
LO BIAS
TO INPUT ATTENUA TOR
ADJ.
J6
3.6 GHz
L.O.
AUX OUT
IF BIAS
-8 dBm
NULLING
2ND LO
POWER
DETECTOR
7.2 GHz
NOTCH
10dB
10dB
10dB
W15
J5
2ND LO
6dB
2ND LO
3.6 GHz, +1dBm
GAIN ADJ.
CF=3.6 GHz
INPUT SIGNAL < 5GHz
A9 2ND LO BOARD
J10
300 MHz 3RD LO,
TO 3RD CONVERTER
C
TEMP. SENSE
3.6 GHz PMYO
5dB
300 MHz
P4
W16
MAIN COIL
(4)
300 MHz
FM
600 MHz
COIL
P3
600 MHz
UNLOCK
X3
J1
INDICATOR
X2
+11 dBm
FAN CONTROL
SAW FILTER
50 MHz CAL.
DOUBLER BIAS
TRIG
TRIG
S
50 MHz CAL
1
2
DETECTOR
(TO 3RD CONVERTER)
OUT
OUT
TO SYNTH BD. VIA
MOTHERBOARD
CPU
J12
J11
10 MHz
FRONT END DRIVER
DIST.
LO SYNTH
ANALOG IF
W13
W14
(20)
(30)
OPTIONS
TO REAR PANEL
W19
NOTE: J4 and W19
321.4 MHz, -30 dBm
not present on E4447A
AUX OUTPUT TO REAR PANEL
(E4446A/E4448A)
J4
3 dB
14 dB
SYSTEM
AUX 321.4 IF
14dB
VARIABLE
200 MHz
OUT AMP
GAIN
321.4 MHz
278.6 NOTCH
BW=10 MHz
3RD MIXER
LPF
14 dB
J5
I
R
12dB
L
PIN
TUNE
21.4 MHz
DIODE
DACS
300 MHz
DRIVE
+21 dBm
321.4 MHz
LINEARIZATION
CAL SIGNAL
5.1 dB
CIRCUIT
7.5 MHz
CAL SIGNAL
MUX
5.5 dB
3RD LO AMPLIFIERS
9.6 dB
I
2.1dB
DET.
300 MHz, +7 dBm
L
LEVEL
21.4 MHz
300 MHz
DAC
AMP
LEVELING LOOP
CAL-OSC, LOW
FROM AIF VIA
300 MHz, +11dBm
MOTHERBOARD
CAL-OSC, HIGH
FROM REFERENCE BD.
J7
J6
VIA MOTHERBOARD
50 MHz
A
D
C
CALIBRATOR
W20
(50)
A8 ANALOG IF
PREFILTERS. BW = 2.5 X RBW
LC BW = 200 kHz TO 7.5 MHz
21.4 MHz AUTO RANGE
XTAL BW = 2.5 kHZ TO 200 kHz
PLL
TO DIF VIA MOTHERBOARD
2 MHz
+7dB
W11
LC
4TH MIXER
(3)
3 dB
J13
R
I
+6
21.4 MHz, -30 dBm
XTAL
L
-3dB
AIF
ANTI ALIAS
MAIN
12.5 MHz
FILTER
-33 dB INPUT
GAIN
BW = 10 MHz
SIGNAL 30 GHz
POWER
10 MHz REF
DETECTOR
PLL
BUFFER
28.9 MHz
244 kHz
4TH LO
FM RATE = 10 Hz
PK DET.
BURST
POWER SUPPLY
-1
SWITCHING
TV FILTER
REFERENCE
BURST TRIGGER THRESHOLD
VERT
TV
AGC
HORIZ
TRIGGER
CALIBRATION
ODD/EVEN
REAR PANEL
ECL
FREQUENCY
VIDEO
EXT. TRIG .
GENERATOR
W12
INVERT
(6)
21.4 MHz
P4
10MHz REF
PLL
INTERP. CAL
TRIG 2
INTERPOLATOR
LEV
CAL OSC
GATE ARM
CAL TRIGGER
W1
LINE
GATE TRIG
TO DIF VIA
TRIGGER
(5)
BURST
MUX
SWEEP ARM
MOTHERBOARD
P1
TV
SWEEP TRIG
30 MHz
3
TRIG 1
PLL
FRONT PANEL
LEV
EXT. TRIG .
Note -
POWER LEVELS BASED ON THESE SETTINGS:
Center Frequency - 50 MHz for Low band, 5 GHz for High band,
30 GHz for mm band. Preselector Centering
Required for Input Signals >3 GHz.
Span - 0 Hz.
Input Attenuation - 10 dB
Preamp - Off
Electronic Attenuator - 0 dB
Auto Align Turned Off After Inital Auto Align
A7 DIGITAL IF
TRIG1,TRIG2
TO 2ND LO BD.
TRIGGER INPUTS
TP5
FROM AIF
2
AUTO RANGE
ATTEN: 0 TO 24 dB
4
PCI BUS
6 dB STEPS
GAIN
(TO CPU BUS)
P7
14
LOOK
DIGITAL IF
BIT
UP
32
ASIC
50 W
6 dB
18 dB
ADC
ADC
DITHER
OFFSET
GENERATOR
2
6 dB
RANGING
RULES
16
SERIAL BUS
RANGE
INTERFACE
DETECTION
30 MHz
TIMING
21.4 MHz
AUTORANGE
J9
P62
W10
(8)
P2
+6
-6dB
7.5 MHz,
A5 POWER SUPPLY
-24 dBm
+5.2 V
-5.2 V
+9 V
+15 V
±5% FM DEVIATION
-15 V
TO POWER SUPPLY
+32 V
VIA MOTHERBOARD
CAL OSC TRIGGER
CAL OSC HI
D
TO 3RD CONVERTER
CAL OSC LO
SWITCHING
LINE
POWER SUPPLY
INTERP
FREQ REF.
TRIGGER.
SHUTDOWN
CAL
TRIGGER
J9
ECL
P55
SAMPLE RATE HI
J9
SAMPLE RATE LO
P54
E4446A/E4447A/E4448A OVERALL BLOCK DIAGRAM
March 28, 2008

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