Agilent Technologies PSA Series Service Manual page 213

E4440A, E4443A and E4445A OVERALL BLOCK DIAGRAM
A14 INPUT ATTENUATOR A A15 INPUT ATTENUATOR B
[50 MHz, -25 dBm]
[50 MHz, -35 dBm]
( 5 GHz, -25 dBm)
( 5 GHz, -35 dBm)
2 dB 2 dB W8 10 dB 6 dB 20 dB 30 dB
RF-INPUT
DC COUPLED 3Hz to f max
W7
AC COUPLED 20MHz to f max
(Coupling not automatic)
f max:
E4440A= 26.5 GHz
W30
E4445A= 13.2 GHz
E4443A= 6.7 GHz
14
W29
W20
PRE-SEL OUT
(REAR PANEL)
10 10
Calibrator Signal A
50 MHz CW, -25 dBm
W47 W26
(97)
A13 FRONT END DRIVER J5 J6 J3 J4 J11
10 kHz ELECTRONIC J13
ATTENUATOR W53
10 Mhz ATTENUATOR
16 CONTROL
REF. CONTROL
BIT
1/N 1/N COUNTER
DAC
N=1-2 N=1-2 32 32 UNPRESELECTED YTO
J7 W25
MIXER CONTROL MAIN COIL
DELAY RYTHM FM COIL
10
BIAS/CTRL
COMP. PASS THRU
YTF TUNE RAMP GENERATOR
THERMOMETER
FROM LO VIA
10 kHz
N=1-2 48 MOTHERBOARD
16 LO
BIT
1/N COUNTER TO 3rd CONVERTER UNLEVEL
DAC VIA MOTHERBOARD
J2
W28
VARIABLE GAIN RAMP GENERATOR
SLODA
+32v LEVELING LOOP
GATE BIAS
28v LOWBAND PREAMP HI/LO SWITCH
REGULATOR BIAS/CONTROL BIAS/CTRL BIAS
J8 J9
W31 W49
TO REAR PANEL
28v (SWITCHED)
B
A12 LO SYNTHESIZER
J1
3-7 GHz
A12 A2 SAMPLING OSCILLATOR DAUGHTER BD.
614-748 MHz
N*600/256+600MHz
J1
F S DUAL PATH LOOP
¦
J3
SINGLE
SAMPLER IF LOOP
OFFSET SAMPLING
PATH
OSC. PLL
90 MHz
R
LPF 1/8
375-875 MHz
RATE L
MULTIPLIER
NARROW SPAN WIDE SPAN
N=6-63
50-70 MHz
(DUAL LOOP) (SINGLE LOOP)
J3
FRAC-N
Divider
J4 1200MHz
NARROW SPAN
X2
600MHz
WIDE SPAN
F
1/R
¦
(600 MHz FROM MOTHERBOARD) R=5, 6, 7 (DUAL LOOP)
129 (SINGLE LOOP)
se81a
FL1
A27 ELECTRONIC ATTENUATOR -35.5 dBm -35.5 dBm
3 GHz, LPF
OPTION B7J
A19 RYTHM [50 MHz, -35 dBm]
W48
J2
IN
W51 W52
0-40 dB IN 1dB STEPS
YTF
W49
Odd/Even IF B
20
W9
W50
W17
J1
YTF Coil
Driver
(321.4 MHz
- 48 ± 1 dBm)
LO 3-7 GHz
(5.3214 GHz, 14 dBm ± 3 dB)
A20 LOWBAND
W38
FIRST MIXER
20
3Hz-3GHz
J1
HIGH/LOW
A21 SLODA
HI
LO DISTRIBUTION AMPLIFIER
LIMITER
A18
[3.9714 GHz, 12-17 dBm] INT. SENSE
LO
(5.3214 GHz, 12-17 dBm)
FIRST LO OUT
W35
3-7 GHz YTO 3-7 GHz
+ 15 dBm
Nominal
EXT. SENSE 10 dB
90
PIN ATTEN. SAMPLER HYBRID
OUT
10 3-7 GHz
-3 TO -8 dBm W41
J2
W24
1ST LO
[3.9714 GHz 3.9-7GHz
14.5 dBm ± 1 dB]
LO OUT to
front panel
W45 W45 W46
(Opt AYZ) (Opt AYZ) (Opt AYZ)
A12 A1 SYNTHESIZER
PRETUNE A11 REFERENCE BOARD
GENERATOR
100 MHz PLL
UNLOCK DETECTOR
W22
DAC
(70)
P1 100 MHz
VCO
F
REAR PANEL 1/R
¦
EXT. REF INPUT
LOOP GAIN
1MHz TO 30MHz
DELAY
COMP
50MHz/N.F.
FRAC-N 1 / 2
MAIN COIL
FILTER
REAR PANEL 1 / 5
10MHz REF OUT
TO FE
EXT. REF OUT OFF
MAIN COIL DRIVER +5dBm
P2
VIA
MOTHERBOARD.
FM COIL
PRETUNE GAIN W21
CONTROL (90)
A22 LOWBAND PREAMP
OPTION 1DS
+20 dB +20 dB
Coax
A10 THIRD CONVERTER
Switch
5 dB 5 dB
EXT. MIXER BIAS
W44 J3
Front Panel
BIAS T
IF IN
(321.4 MHz Nominal
-20 dBm, Max)
(Option AYZ)
0-30 dB
W17 2 dB/STEP
14dB
J1
(10)
W40 W39
FL2
CF = [3.9214 GHz, -33.5 dBm]
[3.9214 GHz, -31 dBm] J2
BW = 40 MHz
OVERLOAD J3 J4
DETECTOR W18
3dB 2dB
(7)
400 MHz
SECOND MIXER
9dB
RING RESONATOR J7
[321.4 MHz IF
1ST IF AMP
-43 dBm + 2 dBm]
50 MHz
FROM
LO BIAS REFERENCE
ADJ. BOARD VIA
J6 3.6 GHz
MOTHERBOARD
AUX OUT
LO IF
-8 dBm
2 dB
BIAS-ADJ.
2ND LO
POWER
I BIAS DETECTOR
7.2 GHz
NOTCH
THERMOMETER
1dB 3dB
10dB
1dB 3dB
2ND LO GAIN ADJ.
TO INPUT ATTENUA TOR
10dB
Q BIAS
LO NULLING
CF=3.6 GHz
J5
J8
2ND LO
3.6 GHz, +3dBm
26
W15
W61 (Option 122)
(65)
W62 (Option 122)
C (95)
100 MHz TO WB A-IF
TO A31 WB A-IF
P5 300 MHz 3RD LO, A9 2ND LO BOARD J10
TO 3RD CONVERTER
TEMP. SENSE
3.6 GHz PMYO 5dB
300 MHz -27 dBm
P4 MAIN COIL
300 MHz FM
600 MHz 600 MHz COIL
P3 J1 UNLOCK
X3 + 13 + 3 dB
W16 INDICATOR
X2
FAN CONTROL
(4)
50 MHz CAL.
DOUBLER BIAS S TRIG TRIG
50 MHz CAL DETECTOR 1 2
(TO 3RD CONVERTER) OUT OUT
CPU
10 MHz FRONT END DRIVER J12 J11
DIST. LO SYNTH
ANALOG IF
TO SYNTH BD.
OPTIONS W13
VIA MOTHERBOARD
(20)
TO REAR PANEL
W65 (Option 122)
(40)
IF OUT TO A31 WB A-IF
W19
(40)
321.4 MHz, -30 dBm + 2 dB
AUX OUTPUT TO REAR PANEL
J6
J4
21.4 MHz
3 dB
14 dB
SYSTEM
AUX 321.4 IF
VARIABLE
200 MHz OUT AMP
14 dB GAIN
321.4 MHz
BW=30 MHz 3RD MIXER +15 dB
J5
14 dB
2ND IF
I
AMP 2
R
2 GHz 2ND IF 2dB
L
PIN AMP 3 21.4 MHz
TUNE
DIODE
DACS 300 MHz
DRIVE +23 dBm
-.5 TO
321.4 MHz
4.5 V LINEARIZATION
CAL SIGNAL 1 dB
CIRCUIT
VARIABLE GAIN
RAMP FROM FE
DRIVER VIA MOTHERBOARD CAL SIGNAL
MUX 2.8 dB
3RD LO AMPLIFIERS
50 MHz CALIBRATOR ALC
9.6 dB
I 2.8 dB
300 MHz, +7 dBm
DET.
L
LEVEL
21.4 MHz
DAC 300 MHz
AMP
LEVELING LOOP CAL-OSC, LOW
FROM AIF VIA
300 MHz, +11dBm
MOTHERBOARD
CAL-OSC, HIGH FROM REFERENCE BD.
J7 J6 VIA MOTHERBOARD
50 MHz CALIBRATOR
A W64 (Option 122) D C
W20 (60)
(50)
CAL SIGNAL FROM A31 WB A-IF
A8 ANALOG IF
LC BW = 200 kHz TO 2.83 MHz
XTAL BW = 2.5 kHZ TO 200 kHz 21.4 MHz AUTO RANGE
PLL
TO DIF VIA MOTHERBOARD
2 MHz
+7dB
LC
W11
4TH MIXER
(3) 3 dB
J13
R I
+6
21.4 MHz, -27 dBm
XTAL -3dB L
+ 2dB AIF
ANTI ALIAS
MAIN
FILTER 12.5 MHz
GAIN
BW = 10 MHz
POWER
PLL 10 MHz REF
DETECTOR
BUFFER
28.9 MHz
4TH LO
DET.
POWER SUPPLY
BURST
SWITCHING
VIDEO REFERENCE
PK DET.
BURST TRIGGER THRESHOLD
AGC
CALIBRATION
REAR PANEL FREQUENCY
EXT. TRIG . GENERATOR
W12
42.8 MHz
(6)
P4
10MHz REF PLL
INTERP. CAL
TRIG 2
CAL OSC GATE ARM
LEV
W1
LINE TRIGGER GATE TRIG TO DIF VIA
(5) BURST SWEEP ARM MOTHERBOARD
MUX
P1 30 MHz
TV SWEEP TRIG
3
W14
TRIG 1 PLL
(30)
LEV
FRONT PANEL
EXT. TRIG .
Note -
POWER LEVELS BASED ON THESE SETTINGS:
Center Frequency - 50 MHz for Low band, 5 GHz for High band,
Preselector Centering Required for Input
Signals >3 GHz.
Span - 0 Hz.
Input Attenuation - 10 dB
Preamp - Off
Electronic Attenuator - 0 dB
Single Sweep
A7 DIGITAL IF
TRIG1,TRIG2
TO 2ND LO BD.
TRIGGER INPUTS
2
TP5 FROM AIF
-20 dBm
AUTO RANGE
ATTEN: 0 TO 24 dB
6 dB STEPS 4 PCI BUS
7.5 MHz
(TO CPU BUS)
+4 dBm GAIN
P1 14 LOOK
MAX
DIGITAL IF 32
BIT UP
ASIC
6 dB 18 dB ADC
50 W
ADC DITHER
OFFSET
GENERATOR
2
6 dB
RANGING
RULES
16
SERIAL BUS
RANGE
INTERFACE
DETECTION
30 MHz
TIMING
21.4 MHz
AUTORANGE
J9
P62
W10
(8)
P2
+6
7.5 MHz, -24 dBm
-6dB
A5 POWER SUPPLY
+ 2dB
+5.2 V
-5.2 V
+9 V
+15 V
244 kHz ±5% FM DEVIATION
-15 V
FM RATE = 10 Hz
TO POWER SUPPLY
+32 V
VIA MOTHERBOARD
CAL OSC TRIGGER
ECL
CAL OSC HI
TO 3RD CONVERTER D
CAL OSC LO
INTERP SWITCHING LINE POWER SUPPLY
INTERPOLATOR FREQ REF. TRIGGER. SHUTDOWN
CAL
CAL TRIGGER
TRIGGER
J9
ECL
P55 SAMPLE RATE HI
E4440A, E4443A and E4445A
J9 SAMPLE RATE LO
P54 OVERALL BLOCK DIAGRAM
March 28, 2008