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(2) Transmit operation
When the UARTCAEn bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin.
Then, when the TXEn bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation
is started by writing transmit data to transmit buffer register n (TXBn).
(a) Transmission enabled state
This state is set by the TXEn bit in the ASIMn register.
• TXEn = 1: Transmission enabled state
• TXEn = 0: Transmission disabled state
Since UARTn does not have a CTS (transmission enabled signal) input pin, a port should be used to
confirm whether the destination is in a reception enabled state.
(b) Starting a transmit operation
In the transmission enabled state, a transmit operation is started by writing transmit data to transmit buffer
register n (TXBn). When a transmit operation is started, the data in TXBn is transferred to the transmit
shift register.
Then, the transmit shift register outputs data to the TXDn pin (the transmit data is
transferred sequentially starting with the start bit). The start bit, parity bit, and stop bits are added
automatically.
(c) Transmission interrupt request
When the transmit shift register becomes empty, a transmission completion interrupt request (INTSTn) is
generated. The timing for generating the INTSTn interrupt differs according to the specification of the stop
bit length. The INTSTn interrupt is generated at the same time that the last stop bit is output.
If the data to be transmitted next has not been written to the TXBn register, the transmit operation is
suspended.
Caution Normally, when the transmit shift register becomes empty, a transmission completion
interrupt (INTSTn) is generated.
(INTSTn) is generated if the transmit shift register becomes empty due to the input of
RESET.
CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User's Manual U15905EJ1V0UD
However, no transmission completion interrupt
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