NEC V850ES/SA2 UPD703201 Manual page 428

INTC accepted
CPU processing
Note For the ISPR register, see 14.3.6 In-service priority register (ISPR).
The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is being
serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally by the interrupt controller. In such case, if the
interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by the RETI and LDSR instructions, input of
the pending INT starts the new maskable interrupt servicing.
428
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 14-4. Maskable Interrupt Servicing
INT input
xxIF = 1
Yes
xxMK = 0
Yes
Priority higher than
that of interrupt currently
being serviced?
Yes
Priority higher
than that of other interrupt
request?
Yes
Highest default
priority of interrupt requests
with the same priority?
Yes
Maskable interrupt request
PSW.NP
0
PSW.ID
0
EIPC Restored PC
EIPSW PSW
ECR.EICC Exception code
PSW.EP 0
PSW.ID 1
Corresponding
Note
bit of ISPR
PC Handler address
Interrupt servicing
Preliminary User's Manual U15905EJ1V0UD
No
No
Is the interrupt
mask released?
No
No
No
Interrupt request held pending
1
1
Interrupt request held pending
1