NEC V850ES/SA2 UPD703201 Manual page 354

COI
0
Addresses do not match.
1 Addresses match.
Condition for clearing (COI = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
TRC
Receive status (other than transmit status). The SDA line is set to high impedance.
0
Transmit status. The value in the SO latch is enabled for output to the SDA line (valid starting
1
at the falling edge of the first byte's ninth clock).
Condition for clearing (TRC = 0)
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• Cleared by WREL = 1
• When ALD changes from 0 to 1
• When RESET is input
Master
• When "1" is output to the first byte's LSB (transfer
direction specification bit)
Slave
• When a start condition is detected
When not used for communication
Note TRC is cleared and the SDA line becomes high impedance when bit 5 (WREL) of the IIC control register
(IICC) is set and the wait state is released at ninth clock when bit 3 (TRC) of the IIC status register (IICS)
= 1.
Remark WREL: Bit 5 of IIC control register (IICC)
LREL: Bit 6 of IIC control register (IICC)
IICE: Bit 7 of IIC control register (IICC)
354
CHAPTER 12 SERIAL INTERFACE FUNCTION
Detection of matching addresses
Detection of transmit/receive status
Note
Preliminary User's Manual U15905EJ1V0UD
Condition for setting (COI = 1)
• When the received address matches the local
address (SVA) (set at the rising edge of the
eighth clock).
Condition for setting (TRC = 1)
Master
• When a start condition is generated
Slave
• When "1" is input by the first byte's LSB (transfer
direction specification bit)
(2/3)