NEC V850ES/SA2 UPD703201 Manual page 76

• Interrupt/exception table
The V850ES/SA2 and V850ES/SA3 speed up the interrupt response time by fixing handler addresses
corresponding to interrupts/exceptions.
A collection of these handler addresses is called an interrupt/exception table, which is mapped to the internal
ROM area. When an interrupt/exception is acknowledged, execution jumps to a handler address and the
program in the area starting from that address is executed. Table 3-3 shows the interrupt/exception sources
and corresponding addresses.
First Address of Interrupt/Exception Table
00000000H
00000010H
00000040H
00000050H
00000060H
00000080H
00000090H
000000A0H
000000B0H
000000C0H
000000D0H
000000E0H
000000F0H
00000100H
00000110H
00000120H
00000130H
00000140H
00000150H
00000160H
00000170H
00000180H
Notes 1. µ PD703201, 703204, 70F3201Y, and 70F3204Y only
2. V850ES/SA3 only
76
CHAPTER 3 CPU FUNCTION
Table 3-3. Interrupt/Exception Table
Interrupt/Exception First Address of Interrupt/Exception Table
Source
RESET 00000190H
NMI 000001A0H
TRAP0n (n = 0 to F) 000001B0H
TRAP1n (n = 0 to F) 000001C0H
ILGOP/DBG0 000001D0H
INTWDTM 000001E0H
INTP0 000001F0H
INTP1 00000200H
INTP2 00000210H
INTP3 00000220H
INTP4 00000230H
INTP5 00000240H
INTP6 00000250H
INTRTC 00000260H
INTCC00 00000270H
INTCC01 00000280H
INTOVF0 00000290H
INTCC10 000002A0H
INTCC11 000002B0H
INTOVF1 000002C0H
INTTM2 000002D0H
INTTM3
Preliminary User's Manual U15905EJ1V0UD
Interrupt/Exception
INTTM4
INTTM5
INTCSI0
INTIIC
INTCSI1
INTSRE0
INTSR0
INTST0
INTCSI2
INTSRE1
INTSR1
INTST1
INTCSI3
INTCSI4
INTAD
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTROV
INTBRG
−
Source
Note 1
Note 2
−