NEC V850ES/SA2 UPD703201 Manual page 236

t
Count
clock
TMn
0000H 0001H
register
Count start
CCn0
p
register
CCn1
q
register
INTCCn0
interrupt
INTCCn1
interrupt
TOn
(output)
Remarks 1. p: Setting value of CCn0 register (0000H to FFFFH)
q: Setting value of CCn1 register (0000H to FFFFH)
p ≠ q
t: Count clock cycle
PWM cycle = 65,536 × t
q
=
Duty
65,536
2. In this example, the active level of the TOn output is set to the high level.
3. n = 0, 1
236
CHAPTER 7 TIMER/COUNTER FUNCTION
Figure 7-12. PWM Output Timing Example
p q
p p
q q
−
p
Preliminary User's Manual U15905EJ1V0UD
FFFFH 0000H 0001H p
Clear
p
q
q
p
q