NEC V850ES/SA2 UPD703201 Manual page 461

(2) Releasing sub-IDLE mode by RESET pin input
The same operation as the normal reset operation is performed.
Setting of Sub-IDLE Mode
Item
Subclock oscillator
CPU
DMA
Interrupt controller
ROM correction
16-bit timer/event counters (TM0, TM1)
8-bit timer/event counters (TM2 to TM5)
Real-timer counter
Watchdog timer
Serial interface CSI0 to CSI4
2 Note
I C
UART0, UART1
A/D converter
D/A converter
External bus interface
Port function
Internal data
Note µ PD703201Y, 703204Y, 70F3201Y, and 70F3204Y only
CHAPTER 15 STANDBY FUNCTION
Table 15-10. Operation Status in Sub-IDLE Mode
When Main Clock Is Oscillating
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable
Stops operation
Operable when SCKn input clock is selected as operation clock (n = 0 to 4)
Stops operation
Stops operation
Stops operation
Stops operation
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before sub-IDLE mode was set.
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the sub-IDLE mode was set.
Preliminary User's Manual U15905EJ1V0UD
Operation Status
When Main Clock Is Stopped
Operable when f is selected as count
XT
clock
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