NEC V850ES/SA2 UPD703201 Manual page 12

12.4.1 Configuration.............................................................................................................................346
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12.4.2 I C control registers ...................................................................................................................348
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12.4.3 I C bus mode functions .............................................................................................................359
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12.4.4 I C bus definitions and control methods ....................................................................................360
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12.4.5 I C interrupt request (INTIIC).....................................................................................................367
12.4.6 Interrupt request (INTIIC) generation timing and wait control ...................................................385
12.4.7 Address match detection method..............................................................................................386
12.4.8 Error detection...........................................................................................................................386
12.4.9 Extension code..........................................................................................................................386
12.4.10 Arbitration..................................................................................................................................387
12.4.11 Wakeup function .......................................................................................................................389
12.4.12 Communication reservation.......................................................................................................390
12.4.13 Cautions ....................................................................................................................................393
12.4.14 Communication operations........................................................................................................394
12.4.15 Timing of data communication ..................................................................................................396
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) .....................................................................403
13.1 Features ...................................................................................................................................403
13.2 Configuration ..........................................................................................................................404
13.3 Control Registers....................................................................................................................405
13.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3).............................................................405
13.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)......................................................406
13.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3) ....................................................................407
13.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)...................................................408
13.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) .......................................................409
13.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) .............................................................410
13.4 DMA Bus States ......................................................................................................................412
13.4.1 Types of bus states ...................................................................................................................412
13.4.2 DMAC bus cycle state transition ...............................................................................................413
13.5 Transfer Mode .........................................................................................................................414
13.5.1 Single transfer mode .................................................................................................................414
13.6 Transfer Types ........................................................................................................................414
13.6.1 Two-cycle transfer.....................................................................................................................414
13.7 Transfer Object .......................................................................................................................415
13.7.1 Transfer type and transfer object ..............................................................................................415
13.7.2 External bus cycles during DMA transfer (two-cycle transfer)...................................................415
13.8 DMA Channel Priorities ..........................................................................................................416
13.9 DMA Transfer Start Factors ...................................................................................................416
13.10 DMA Transfer End...................................................................................................................416
13.10.1 DMA transfer end interrupt ........................................................................................................416
13.10.2 Terminal count output upon DMA transfer end .........................................................................416
13.11 Precautions .............................................................................................................................417
13.11.1 Interrupt factors .........................................................................................................................417
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION ................................................418
14.1 Features ...................................................................................................................................418
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Preliminary User's Manual U15905EJ1V0UD