NEC V850ES/SA2 UPD703201 Manual page 353

(2) IIC status register (IICS)
The IICS register is used to indicate the status of I
The IICS register can be set by an 8-bit or 1-bit memory manipulation instruction. IICS is a read-only register.
RESET input clears the IICS register to 00H.
After reset: 00H R
IICS MSTS ALD
MSTS
0 Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTS = 0)
• When a stop condition is detected
• When ALD = 1
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
ALD
0
This status means either that there was no arbitration or that the arbitration result was a "win".
1 This status indicates the arbitration result was a "loss". MSTS is cleared.
Condition for clearing (ALD = 0)
• Automatically cleared after IICS is read
• When IICE changes from 1 to 0
• When RESET is input
EXC
0 Extension code was not received.
1
Extension code was received.
Condition for clearing (EXC = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICS.
Remark LREL: Bit 6 of IIC control register (IICC)
IICE: Bit 7 of IIC control register (IICC)
CHAPTER 12 SERIAL INTERFACE FUNCTION
2
Address: FFFFFD86H
EXC COI TRC
Detection of arbitration loss
Note
Detection of extension code reception
Preliminary User's Manual U15905EJ1V0UD
C.
ACKD STD SPD
Master device status
Condition for setting (MSTS = 1)
• When a start condition is generated
Condition for setting (ALD = 1)
• When the arbitration result is a "loss".
Condition for setting (EXC = 1)
• When the higher four bits of the received address
data is either "0000" or "1111" (set at the rising
edge of the eighth clock).
(1/3)
353