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(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
Processing by master device
IIC
IIC
ACKD
STD
SPD
WTIM
H
ACKE
H
MSTS
STT
L
SPT
WREL
INTIIC
TRC
Transfer lines
SCL
SDA
AD6 AD5 AD4 AD3 AD2 AD1 AD0
Start condition
Processing by slave device
IIC
ACKD
STD
SPD
WTIM
H
H
ACKE
L
MSTS
STT
L
L
SPT
L
WREL
INTIIC
TRC
Note To cancel slave wait, write FFH to IIC or set WREL.
400
CHAPTER 12 SERIAL INTERFACE FUNCTION
Figure 12-39. Example of Slave to Master Communication
(a) Start condition ~ address
←
address
1
2
3
4
5
6
Preliminary User's Manual U15905EJ1V0UD
IIC
7
8
9
1
R
D7
←
IIC
data
←
FFH Note
Note
2
3
4
5
6
D6
D5
D4
D3
D2
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