NEC V850ES/SA2 UPD703201 Manual page 356

(3) IIC clock selection register (IICCL)
The IICCL register is used to set the transfer clock for I
The IICCL register can be set by an 8-bit or 1-bit memory manipulation instruction. Set the SMC, CL1, and
CL0 bits in combination with the CLX bit of the IIC function expansion register (IICX) (see Table 12-6
Selection Clock Setting).
RESET input clears the IICCL register to 00H.
After reset: 00H R/W
IICCL 0
CLD
0 SCL line was detected at low level.
1 SCL line was detected at high level.
Condition for clearing (CLD = 0)
• When the SCL line is low level
• When IICE = 0
• When RESET is input
DAD
0
SDA line was detected at low level.
1 SDA line was detected at high level.
Condition for clearing (DAD = 0)
• When the SDA line is low level
• When IICE = 0
• When RESET is input
SMC
0
Operates in standard mode.
1
Operates in high-speed mode.
DFC
0
Digital filter off.
1
Digital filter on.
The digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC switching (on/off).
Note Bits 4 and 5 are read-only bits.
Remark IICE: Bit 7 of IIC control register (IICC)
356
CHAPTER 12 SERIAL INTERFACE FUNCTION
Note
Address: FFFFFD84H
0 CLD DAD
Detection of SCL line level (valid only when IICE = 1)
Detection of SDA line level (valid only when IICE = 1)
Preliminary User's Manual U15905EJ1V0UD
2
C.
SMC DFC CL1
Condition for setting (CLD = 1)
• When the SCL0 line is high level
Condition for setting (DAD = 1)
• When the SDA line is high level
Operation mode switching
Digital filter operation control
CL0