Controlling Interrupt Request Signal Output; Notes - NEC V850ES/SA2 UPD703201 Manual

8.3.3

Controlling interrupt request signal output

This section explains how to control interrupt request signals, taking INTS0 to INTS3 = 0111B (every second) and
INTS0 to INTS3 = 1000B (every minute) as an example.
<1> When the RESET input signal is asserted (0), the values of the RTCC0 and RTCC1 registers are initialized.
Real-time counter clock operation is enabled when RTCAE is set to 1, and real-time counter count operation
is enabled when RTCE is set to 1.
<2> Clear RTCAE to 0 and select the CKS bit.
<3> The internal clock operation is started when RTCAE = 1.
<4> After 3 internal clocks, the value of all the count setting registers are reflected on the corresponding count
registers at all once, and the real-time counter starts counting up.
<5> Set the INTS0 to INTS3 bits to 0111B (1000B).
<6> Because INTS0 to INTS3 = 0111B, the INTRTC signal is asserted each time 1 second is counted (because
INTS0 to INTS3 = 1000B, the INTRTC signal is asserted each time 1 minute is counted).
<7> The INTROV signal is asserted when the overflow conditions of all the count registers have been satisfied.
8.3.4

Notes

(1) When the reset signal is input, the CKS bit of RTC control register 0 (RTCC0) is cleared to 0. Therefore, the
real-time counter operates with the subclock (f
• To continue the real-time counter operation even during the reset period, select f
clock. If the prescaler 3 clock (f
reset input, in which case the operation cannot be guaranteed.
• If the real-time counter is not used, clear RTCAE of the RTCC0 register to 0 after the reset signal has been
cleared.
(2) Perform initialization after clearing RTCAE to 0 when the reset signal has been cleared for the first time. For
initialization, set each count setting register, count clock, and interrupt request signal generation timing using
the procedure described in (4) and (5) below, and clear the OVFIF bit of the OVFIC register and the RTCIF bit
of the RTCIC register to 0.
(3) Read each count register using the following procedure:
<1> Read the second, minute, hour, day, and week count registers in that order, and then read the second
count register again.
<2> Compare the value of the second count register read first with the value of the second count register read
second.
If the two values do not match, the chances are that the counter counted up while it was being read. If
so, repeat steps <1> and <2> again.
CHAPTER 8 REAL-TIME COUNTER FUNCTION
). Note the following points.
XT
) (CKS = 1) is selected, the count clock is changed to f
BRG
Preliminary User's Manual U15905EJ1V0UD
(CKS = 0) as the count
XT
(CKS = 0) by the
XT
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