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(3) Block diagram
WR
PMC
Output enable signal of AD0 to AD15
WR
PM
Output buffer OFF signal
Output of AD0 to AD15
WR
PORT
Input enable signal
RD
Remarks 1. PDL:
Port register DL
PMDL:
Port mode register DL
PMCDL: Port mode control register DL
Output buffer OFF signal: Signal that is active in IDLE/STOP mode
2. n = 0 to 15
CHAPTER 4 PORT FUNCTIONS
Figure 4-33. Block Diagram of PDL0 to PDL15
PMCDL
PMCDLn
PMDL
PMDLn
PDL
PDLn
Address
of AD0 to AD15
Input of AD0 to AD15
Preliminary User's Manual U15905EJ1V0UD
PDL0/AD0 to
PDL15/AD15
173
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