NEC V850ES/SA2 UPD703201 Manual page 277

(3) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operation mode and enables/disables count operations.
This register is a special register that can be written only in a special sequence (refer to 3.4.8 Special
registers).
The WDTM register is set by an 8-bit or 1-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
After reset: 00H
< >
WDTM RUN
RUN
0
1
WDTM4
0
0
1
1
Notes 1. Once the RUN bit is set (to 1), it cannot be cleared (to 0) by software.
Therefore, when counting is started, it cannot be stopped except through RESET input.
2. Once the WDTM3 and WDTM4 bits are set (to 1), they cannot be cleared (to 0) by software and can
be cleared only through RESET input.
CHAPTER 9 WATCHDOG TIMER FUNCTIONS
R/W Address: FFFFF6C2H
0 0 WDTM4
Selection of watchdog timer operation mode
Stops counting
Clears counter and starts counting
WDTM3 Selection of watchdog timer operation mode
0
Interval timer mode
1
(Upon overflow, maskable interrupt INTWDTM is generated.)
0
Watchdog timer mode 1
(Upon overflow, non-maskable interrupt INTWDT is generated.)
1
Watchdog timer mode 2
(Upon overflow, reset operation WDTRES is started.)
Preliminary User's Manual U15905EJ1V0UD
WDTM3 0 0
Note 1
Note 2
0
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